Searched refs:TRAINING_SW_1_REG (Results 1 – 5 of 5) sorted by relevance
| /drivers/ddr/marvell/a38x/ |
| A D | mv_ddr_regs.h | 245 #define TRAINING_SW_1_REG 0x15b4 macro
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| A D | mv_ddr4_training_leveling.c | 430 TRAINING_SW_1_REG, 0x1 << 16, 0x1 << 16); in mv_ddr4_dynamic_pb_wl_supp()
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| A D | ddr3_training_leveling.c | 249 TRAINING_SW_1_REG, (1 << 16), (1 << 16))); in ddr3_tip_dynamic_read_leveling()
728 TRAINING_SW_1_REG, (1 << 16), (1 << 16))); in ddr3_tip_dynamic_per_bit_read_leveling()
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| /drivers/ddr/marvell/a38x/old/ |
| A D | ddr3_training_ip_flow.h | 129 #define TRAINING_SW_1_REG 0x15b4 macro
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| A D | ddr3_training_leveling.c | 126 TRAINING_SW_1_REG, 1 << 16, 1 << 16)); in ddr3_tip_dynamic_read_leveling()
374 TRAINING_SW_1_REG, (1 << 16), (1 << 16))); in ddr3_tip_dynamic_read_leveling()
881 TRAINING_SW_1_REG, (1 << 16), (1 << 16))); in ddr3_tip_dynamic_per_bit_read_leveling()
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