Searched refs:TRAINING_SW_2_REG (Results 1 – 8 of 8) sorted by relevance
| /drivers/ddr/marvell/a38x/ |
| A D | mv_ddr4_training_leveling.c | 121 TRAINING_SW_2_REG, 0x0, 0x100); in mv_ddr4_xsb_comp_test()
127 TRAINING_SW_2_REG, 0x3, 0x3); in mv_ddr4_xsb_comp_test()
290 TRAINING_SW_2_REG, 0x100, 0x100); in mv_ddr4_dynamic_pb_wl_supp()
296 TRAINING_SW_2_REG, 0x0, 0x3); in mv_ddr4_dynamic_pb_wl_supp()
318 TRAINING_SW_2_REG, 0x0, 0x100); in mv_ddr4_dynamic_pb_wl_supp()
399 TRAINING_SW_2_REG, 0x100, 0x100); in mv_ddr4_dynamic_pb_wl_supp()
413 TRAINING_SW_2_REG, 0x100, 0x100); in mv_ddr4_dynamic_pb_wl_supp()
419 TRAINING_SW_2_REG, 0x0, 0x3); in mv_ddr4_dynamic_pb_wl_supp()
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| A D | ddr3_training_leveling.c | 165 TRAINING_SW_2_REG, 0x1, 0x9)); in ddr3_tip_dynamic_read_leveling()
246 TRAINING_SW_2_REG, (1 << 3), (1 << 3))); in ddr3_tip_dynamic_read_leveling()
537 TRAINING_SW_2_REG, 0x1, 0x9)); in ddr3_tip_dynamic_per_bit_read_leveling()
725 TRAINING_SW_2_REG, (1 << 3), (1 << 3))); in ddr3_tip_dynamic_per_bit_read_leveling()
1023 TRAINING_SW_2_REG, 0x5, 0x7)); in ddr3_tip_dynamic_write_leveling()
1028 TRAINING_SW_2_REG, 0x4, 0x7)); in ddr3_tip_dynamic_write_leveling()
1468 TRAINING_SW_2_REG, 0x1, 0x5)); in ddr3_tip_dynamic_write_leveling_seq()
1761 ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id, TRAINING_SW_2_REG, in mv_ddr_rl_dqs_burst()
1768 ddr3_tip_if_write(0, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, TRAINING_SW_2_REG, in mv_ddr_rl_dqs_burst()
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| A D | mv_ddr_regs.h | 247 #define TRAINING_SW_2_REG 0x15b8 macro
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| A D | ddr3_training.c | 891 TRAINING_SW_2_REG, 0x100, 0x100)); in ddr3_pre_algo_config()
899 TRAINING_SW_2_REG, 0x0, 0x2)); in ddr3_pre_algo_config()
923 TRAINING_SW_2_REG, 0x0, 0x100)); in ddr3_post_algo_config()
1968 if_id, TRAINING_SW_2_REG, in ddr3_tip_reset_fifo_ptr()
1983 if_id, TRAINING_SW_2_REG, in ddr3_tip_reset_fifo_ptr()
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| /drivers/ddr/marvell/a38x/old/ |
| A D | ddr3_hws_hw_training.c | 52 TRAINING_SW_2_REG, 0x100, 0x100)); in ddr3_pre_algo_config()
60 TRAINING_SW_2_REG, 0x0, 0x2)); in ddr3_pre_algo_config()
83 TRAINING_SW_2_REG, 0x0, 0x100)); in ddr3_post_algo_config()
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| A D | ddr3_training_leveling.c | 123 TRAINING_SW_2_REG, 0x8, 0x9)); in ddr3_tip_dynamic_read_leveling()
264 TRAINING_SW_2_REG, 0x1, 0x9)); in ddr3_tip_dynamic_read_leveling()
371 TRAINING_SW_2_REG, (1 << 3), (1 << 3))); in ddr3_tip_dynamic_read_leveling()
663 TRAINING_SW_2_REG, 0x1, 0x9)); in ddr3_tip_dynamic_per_bit_read_leveling()
878 TRAINING_SW_2_REG, (1 << 3), (1 << 3))); in ddr3_tip_dynamic_per_bit_read_leveling()
1176 TRAINING_SW_2_REG, 0x5, 0x7)); in ddr3_tip_dynamic_write_leveling()
1181 TRAINING_SW_2_REG, 0x4, 0x7)); in ddr3_tip_dynamic_write_leveling()
1670 TRAINING_SW_2_REG, 0x1, 0x5)); in ddr3_tip_dynamic_write_leveling_seq()
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| A D | ddr3_training_ip_flow.h | 130 #define TRAINING_SW_2_REG 0x15b8 macro
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| A D | ddr3_training.c | 1850 if_id, TRAINING_SW_2_REG, in ddr3_tip_reset_fifo_ptr()
1865 if_id, TRAINING_SW_2_REG, in ddr3_tip_reset_fifo_ptr()
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