1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
4 */
5
6 #include <clk.h>
7 #include <dm.h>
8 #include <errno.h>
9 #include <watchdog.h>
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/clock.h>
12 #include <asm/global_data.h>
13 #include <dm/platform_data/serial_mxc.h>
14 #include <serial.h>
15 #include <linux/compiler.h>
16 #include <linux/delay.h>
17
18 /* UART Control Register Bit Fields.*/
19 #define URXD_CHARRDY (1<<15)
20 #define URXD_ERR (1<<14)
21 #define URXD_OVRRUN (1<<13)
22 #define URXD_FRMERR (1<<12)
23 #define URXD_BRK (1<<11)
24 #define URXD_PRERR (1<<10)
25 #define URXD_RX_DATA (0xFF)
26 #define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
27 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
28 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
29 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
30 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
31 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
32 #define UCR1_IREN (1<<7) /* Infrared interface enable */
33 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
34 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
35 #define UCR1_SNDBRK (1<<4) /* Send break */
36 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
37 #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
38 #define UCR1_DOZE (1<<1) /* Doze */
39 #define UCR1_UARTEN (1<<0) /* UART enabled */
40 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
41 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
42 #define UCR2_CTSC (1<<13) /* CTS pin control */
43 #define UCR2_CTS (1<<12) /* Clear to send */
44 #define UCR2_ESCEN (1<<11) /* Escape enable */
45 #define UCR2_PREN (1<<8) /* Parity enable */
46 #define UCR2_PROE (1<<7) /* Parity odd/even */
47 #define UCR2_STPB (1<<6) /* Stop */
48 #define UCR2_WS (1<<5) /* Word size */
49 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
50 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
51 #define UCR2_RXEN (1<<1) /* Receiver enabled */
52 #define UCR2_SRST (1<<0) /* SW reset */
53 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
54 #define UCR3_PARERREN (1<<12) /* Parity enable */
55 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
56 #define UCR3_DSR (1<<10) /* Data set ready */
57 #define UCR3_DCD (1<<9) /* Data carrier detect */
58 #define UCR3_RI (1<<8) /* Ring indicator */
59 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
60 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
61 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
62 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
63 #define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
64 #define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
65
66 /* imx8 names these bitsfields instead: */
67 #define UCR3_DTRDEN BIT(3) /* bit not used in this chip */
68 #define UCR3_RXDMUXSEL BIT(2) /* RXD muxed input selected; 'should always be set' */
69
70 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
71 #define UCR3_BPEN (1<<0) /* Preset registers enable */
72 #define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
73 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
74 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
75 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
76 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
77 #define UCR4_IRSC (1<<5) /* IR special case */
78 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
79 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
80 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
81 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
82 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
83 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
84 #define UFCR_RFDIV_SHF 7 /* Reference freq divider shift */
85 #define RFDIV 4 /* divide input clock by 2 */
86 #define UFCR_DCEDTE (1<<6) /* DTE mode select */
87 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
88 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
89 #define USR1_RTSS (1<<14) /* RTS pin status */
90 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
91 #define USR1_RTSD (1<<12) /* RTS delta */
92 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
93 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
94 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
95 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
96 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
97 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
98 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
99 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
100 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
101 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
102 #define USR2_IDLE (1<<12) /* Idle condition */
103 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
104 #define USR2_WAKE (1<<7) /* Wake */
105 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
106 #define USR2_TXDC (1<<3) /* Transmitter complete */
107 #define USR2_BRCD (1<<2) /* Break condition */
108 #define USR2_ORE (1<<1) /* Overrun error */
109 #define USR2_RDR (1<<0) /* Recv data ready */
110 #define UTS_FRCPERR (1<<13) /* Force parity error */
111 #define UTS_LOOP (1<<12) /* Loop tx and rx */
112 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
113 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
114 #define UTS_TXFULL (1<<4) /* TxFIFO full */
115 #define UTS_RXFULL (1<<3) /* RxFIFO full */
116 #define UTS_SOFTRS (1<<0) /* Software reset */
117 #define TXTL 2 /* reset default */
118 #define RXTL 1 /* reset default */
119
120 DECLARE_GLOBAL_DATA_PTR;
121
122 struct mxc_uart {
123 u32 rxd;
124 u32 spare0[15];
125
126 u32 txd;
127 u32 spare1[15];
128
129 u32 cr1;
130 u32 cr2;
131 u32 cr3;
132 u32 cr4;
133
134 u32 fcr;
135 u32 sr1;
136 u32 sr2;
137 u32 esc;
138
139 u32 tim;
140 u32 bir;
141 u32 bmr;
142 u32 brc;
143
144 u32 onems;
145 u32 ts;
146 };
147
_mxc_serial_flush(struct mxc_uart * base)148 static void _mxc_serial_flush(struct mxc_uart *base)
149 {
150 unsigned int timeout = 4000;
151
152 if (!(readl(&base->cr1) & UCR1_UARTEN) ||
153 !(readl(&base->cr2) & UCR2_TXEN))
154 return;
155
156 while (!(readl(&base->sr2) & USR2_TXDC) && --timeout)
157 udelay(1);
158 }
159
_mxc_serial_init(struct mxc_uart * base,int use_dte)160 static void _mxc_serial_init(struct mxc_uart *base, int use_dte)
161 {
162 _mxc_serial_flush(base);
163
164 writel(0, &base->cr1);
165 writel(0, &base->cr2);
166
167 while (!(readl(&base->cr2) & UCR2_SRST));
168
169 if (use_dte)
170 writel(0x404 | UCR3_ADNIMP, &base->cr3);
171 else
172 writel(0x704 | UCR3_ADNIMP, &base->cr3);
173
174 writel(0x704 | UCR3_ADNIMP, &base->cr3);
175 writel(0x8000, &base->cr4);
176 writel(0x2b, &base->esc);
177 writel(0, &base->tim);
178
179 writel(0, &base->ts);
180 }
181
_mxc_serial_setbrg(struct mxc_uart * base,unsigned long clk,unsigned long baudrate,bool use_dte)182 static void _mxc_serial_setbrg(struct mxc_uart *base, unsigned long clk,
183 unsigned long baudrate, bool use_dte)
184 {
185 u32 tmp;
186
187 _mxc_serial_flush(base);
188
189 tmp = RFDIV << UFCR_RFDIV_SHF;
190 if (use_dte)
191 tmp |= UFCR_DCEDTE;
192 else
193 tmp |= (TXTL << UFCR_TXTL_SHF) | (RXTL << UFCR_RXTL_SHF);
194 writel(tmp, &base->fcr);
195
196 writel(0xf, &base->bir);
197 writel(clk / (2 * baudrate), &base->bmr);
198
199 writel(UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST,
200 &base->cr2);
201
202 /*
203 * setting the baudrate triggers a reset, returning cr3 to its
204 * reset value but UCR3_RXDMUXSEL "should always be set."
205 * according to the imx8 reference-manual
206 */
207 writel(readl(&base->cr3) | UCR3_RXDMUXSEL, &base->cr3);
208
209 writel(UCR1_UARTEN, &base->cr1);
210 }
211
212 #if !CONFIG_IS_ENABLED(DM_SERIAL)
213
214 #ifndef CFG_MXC_UART_BASE
215 #error "define CFG_MXC_UART_BASE to use the MXC UART driver"
216 #endif
217
218 #define mxc_base ((struct mxc_uart *)CFG_MXC_UART_BASE)
219
mxc_serial_setbrg(void)220 static void mxc_serial_setbrg(void)
221 {
222 u32 clk = imx_get_uartclk();
223
224 if (!gd->baudrate)
225 gd->baudrate = CONFIG_BAUDRATE;
226
227 _mxc_serial_setbrg(mxc_base, clk, gd->baudrate, false);
228 }
229
mxc_serial_getc(void)230 static int mxc_serial_getc(void)
231 {
232 while (readl(&mxc_base->ts) & UTS_RXEMPTY)
233 schedule();
234 return (readl(&mxc_base->rxd) & URXD_RX_DATA); /* mask out status from upper word */
235 }
236
mxc_serial_putc(const char c)237 static void mxc_serial_putc(const char c)
238 {
239 /* If \n, also do \r */
240 if (c == '\n')
241 serial_putc('\r');
242
243 /* wait for transmitter to be ready */
244 while (readl(&mxc_base->ts) & UTS_TXFULL)
245 schedule();
246
247 writel(c, &mxc_base->txd);
248 }
249
250 /* Test whether a character is in the RX buffer */
mxc_serial_tstc(void)251 static int mxc_serial_tstc(void)
252 {
253 /* If receive fifo is empty, return false */
254 if (readl(&mxc_base->ts) & UTS_RXEMPTY)
255 return 0;
256 return 1;
257 }
258
259 /*
260 * Initialise the serial port with the given baudrate. The settings
261 * are always 8 data bits, no parity, 1 stop bit, no start bits.
262 */
mxc_serial_init(void)263 static int mxc_serial_init(void)
264 {
265 _mxc_serial_init(mxc_base, false);
266
267 serial_setbrg();
268
269 return 0;
270 }
271
mxc_serial_stop(void)272 static int mxc_serial_stop(void)
273 {
274 _mxc_serial_flush(mxc_base);
275
276 return 0;
277 }
278
279 static struct serial_device mxc_serial_drv = {
280 .name = "mxc_serial",
281 .start = mxc_serial_init,
282 .stop = mxc_serial_stop,
283 .setbrg = mxc_serial_setbrg,
284 .putc = mxc_serial_putc,
285 .puts = default_serial_puts,
286 .getc = mxc_serial_getc,
287 .tstc = mxc_serial_tstc,
288 };
289
mxc_serial_initialize(void)290 void mxc_serial_initialize(void)
291 {
292 serial_register(&mxc_serial_drv);
293 }
294
default_serial_console(void)295 __weak struct serial_device *default_serial_console(void)
296 {
297 return &mxc_serial_drv;
298 }
299 #endif
300
301 #if CONFIG_IS_ENABLED(DM_SERIAL)
302
mxc_serial_setbrg(struct udevice * dev,int baudrate)303 int mxc_serial_setbrg(struct udevice *dev, int baudrate)
304 {
305 struct mxc_serial_plat *plat = dev_get_plat(dev);
306 u32 clk = imx_get_uartclk();
307
308 _mxc_serial_setbrg(plat->reg, clk, baudrate, plat->use_dte);
309
310 return 0;
311 }
312
mxc_serial_probe(struct udevice * dev)313 static int mxc_serial_probe(struct udevice *dev)
314 {
315 struct mxc_serial_plat *plat = dev_get_plat(dev);
316 #if CONFIG_IS_ENABLED(CLK_CCF)
317 int ret;
318
319 ret = clk_get_bulk(dev, &plat->clks);
320 if (ret)
321 return ret;
322
323 ret = clk_enable_bulk(&plat->clks);
324 if (ret)
325 return ret;
326 #endif
327 _mxc_serial_init(plat->reg, plat->use_dte);
328
329 return 0;
330 }
331
mxc_serial_getc(struct udevice * dev)332 static int mxc_serial_getc(struct udevice *dev)
333 {
334 struct mxc_serial_plat *plat = dev_get_plat(dev);
335 struct mxc_uart *const uart = plat->reg;
336
337 if (readl(&uart->ts) & UTS_RXEMPTY)
338 return -EAGAIN;
339
340 return readl(&uart->rxd) & URXD_RX_DATA;
341 }
342
mxc_serial_putc(struct udevice * dev,const char ch)343 static int mxc_serial_putc(struct udevice *dev, const char ch)
344 {
345 struct mxc_serial_plat *plat = dev_get_plat(dev);
346 struct mxc_uart *const uart = plat->reg;
347
348 if (readl(&uart->ts) & UTS_TXFULL)
349 return -EAGAIN;
350
351 writel(ch, &uart->txd);
352
353 return 0;
354 }
355
mxc_serial_pending(struct udevice * dev,bool input)356 static int mxc_serial_pending(struct udevice *dev, bool input)
357 {
358 struct mxc_serial_plat *plat = dev_get_plat(dev);
359 struct mxc_uart *const uart = plat->reg;
360 uint32_t sr2 = readl(&uart->sr2);
361
362 if (input)
363 return sr2 & USR2_RDR ? 1 : 0;
364 else
365 return sr2 & USR2_TXDC ? 0 : 1;
366 }
367
368 static const struct dm_serial_ops mxc_serial_ops = {
369 .putc = mxc_serial_putc,
370 .pending = mxc_serial_pending,
371 .getc = mxc_serial_getc,
372 .setbrg = mxc_serial_setbrg,
373 };
374
375 #if CONFIG_IS_ENABLED(OF_CONTROL)
mxc_serial_of_to_plat(struct udevice * dev)376 static int mxc_serial_of_to_plat(struct udevice *dev)
377 {
378 struct mxc_serial_plat *plat = dev_get_plat(dev);
379 fdt_addr_t addr;
380
381 addr = dev_read_addr(dev);
382 if (addr == FDT_ADDR_T_NONE)
383 return -EINVAL;
384
385 plat->reg = (struct mxc_uart *)addr;
386
387 plat->use_dte = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
388 "fsl,dte-mode");
389 return 0;
390 }
391
392 static const struct udevice_id mxc_serial_ids[] = {
393 { .compatible = "fsl,imx21-uart" },
394 { .compatible = "fsl,imx53-uart" },
395 { .compatible = "fsl,imx6sx-uart" },
396 { .compatible = "fsl,imx6ul-uart" },
397 { .compatible = "fsl,imx7d-uart" },
398 { .compatible = "fsl,imx6q-uart" },
399 { }
400 };
401 #endif
402
403 U_BOOT_DRIVER(serial_mxc) = {
404 .name = "serial_mxc",
405 .id = UCLASS_SERIAL,
406 #if CONFIG_IS_ENABLED(OF_CONTROL)
407 .of_match = mxc_serial_ids,
408 .of_to_plat = mxc_serial_of_to_plat,
409 .plat_auto = sizeof(struct mxc_serial_plat),
410 #endif
411 .probe = mxc_serial_probe,
412 .ops = &mxc_serial_ops,
413 .flags = DM_FLAG_PRE_RELOC,
414 };
415 #endif
416
417 #ifdef CONFIG_DEBUG_UART_MXC
418 #include <debug_uart.h>
419
_debug_uart_init(void)420 static inline void _debug_uart_init(void)
421 {
422 struct mxc_uart *base = (struct mxc_uart *)CONFIG_VAL(DEBUG_UART_BASE);
423
424 _mxc_serial_init(base, false);
425 _mxc_serial_setbrg(base, CONFIG_DEBUG_UART_CLOCK,
426 CONFIG_BAUDRATE, false);
427 }
428
_debug_uart_putc(int ch)429 static inline void _debug_uart_putc(int ch)
430 {
431 struct mxc_uart *base = (struct mxc_uart *)CONFIG_VAL(DEBUG_UART_BASE);
432
433 while (!(readl(&base->ts) & UTS_TXEMPTY))
434 schedule();
435
436 writel(ch, &base->txd);
437 }
438
439 DEBUG_UART_FUNCS
440
441 #endif
442