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Searched refs:USB30_PRIM_MASTER_CLK_CMD_RCGR (Results 1 – 7 of 7) sorted by relevance

/drivers/clk/qcom/
A Dclock-sa8775p.c19 #define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf020 macro
36 clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR, in sa8775p_set_rate()
A Dclock-qcs8300.c18 #define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf020 macro
35 clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR, in qcs8300_set_rate()
A Dclock-qcs615.c19 #define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf01c macro
51 clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR, in qcs615_set_rate()
A Dclock-sdm845.c23 #define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf018 macro
153 clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR, in sdm845_clk_enable()
A Dclock-sc7280.c19 #define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf020 macro
52 clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR, in sc7280_set_rate()
A Dclock-sm8150.c24 #define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf01c macro
114 clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR, in sm8150_clk_set_rate()
A Dclock-sm8250.c25 #define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf020 macro

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