| /drivers/ddr/marvell/a38x/ |
| A D | ddr3_training_pbs.c | 87 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, pup); in ddr3_tip_pbs() 100 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, pup); in ddr3_tip_pbs() 176 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, pup); in ddr3_tip_pbs() 335 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, pup); in ddr3_tip_pbs() 350 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, pup); in ddr3_tip_pbs() 373 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, pup); in ddr3_tip_pbs() 400 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, pup); in ddr3_tip_pbs() 461 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, pup); in ddr3_tip_pbs() 478 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, pup); in ddr3_tip_pbs() 627 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, pup); in ddr3_tip_pbs() [all …]
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| A D | ddr3_debug.c | 163 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id); in ddr3_tip_reg_dump() 174 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id); in ddr3_tip_reg_dump() 604 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id); in ddr3_tip_print_stability_log() 818 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id); in ddr3_tip_read_adll_value() 852 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id); in ddr3_tip_write_adll_value() 883 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id); in read_phase_value() 911 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id); in write_leveling_value() 1006 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, j); in print_adll() 1022 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, j); in print_ph() 1176 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, pup); in ddr3_tip_run_sweep_test() [all …]
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| A D | ddr3_training_leveling.c | 206 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_num); in ddr3_tip_dynamic_read_leveling() 272 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_num); in ddr3_tip_dynamic_read_leveling() 420 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_num); in ddr3_tip_dynamic_per_bit_read_leveling() 651 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, in ddr3_tip_dynamic_per_bit_read_leveling() 683 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_num); in ddr3_tip_dynamic_per_bit_read_leveling() 784 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt); in ddr3_tip_calc_cs_mask() 1185 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id); in ddr3_tip_dynamic_write_leveling_supp() 1509 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id); in ddr3_tip_dynamic_write_leveling_seq() 1551 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id); in ddr3_tip_dynamic_read_leveling_seq() 1615 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id); in ddr3_tip_print_wl_supp_result() [all …]
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| A D | mv_ddr4_training_calibration.c | 154 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, subphy_num); in mv_ddr4_dq_vref_calibration() 242 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, subphy_num); in mv_ddr4_dq_vref_calibration() 1189 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, subphy); in mv_ddr4_tap_tuning() 1331 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, subphy); in mv_ddr4_tap_tuning() 1506 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, subphy); in mv_ddr4_tap_tuning() 1527 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, subphy); in mv_ddr4_tap_tuning() 2062 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, subphy); in mv_ddr4_dm_tuning() 2071 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, subphy); in mv_ddr4_dm_tuning() 2100 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, subphy); in mv_ddr4_dm_tuning() 2301 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, subphy); in mv_ddr4_dm_tuning() [all …]
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| A D | ddr3_training_centralization.c | 112 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id); in ddr3_tip_centralization() 142 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id); in ddr3_tip_centralization() 386 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id); in ddr3_tip_centralization() 581 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, pup_id); in ddr3_tip_special_rx() 742 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id); in ddr3_tip_print_centralization_result()
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| A D | ddr3_training_hw_algo.c | 238 VALIDATE_BUS_ACTIVE in ddr3_tip_vref() 263 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, pup); in ddr3_tip_vref() 277 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, pup); in ddr3_tip_vref() 605 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, pup); in ddr3_tip_vref()
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| A D | mv_ddr_topology.c | 216 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, sphy); in mv_ddr_cs_num_get() 271 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, i); in mv_ddr_mem_sz_per_cs_get()
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| A D | ddr3_training_ip_engine.c | 897 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, pup_cnt); in ddr3_tip_read_training_result() 1312 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, sybphy_id); in ddr3_tip_ip_training_wrapper() 1433 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, sybphy_id); in ddr3_tip_ip_training_wrapper() 1470 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, sybphy_id); in ddr3_tip_ip_training_wrapper() 1500 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, sybphy_id); in ddr3_tip_ip_training_wrapper() 1548 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, sybphy_id); in ddr3_tip_ip_training_wrapper() 1615 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt); in ddr3_tip_load_phy_values() 1706 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, in ddr3_tip_training_ip_test()
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| A D | ddr3_training.c | 216 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, sphy); in ddr3_tip_pad_inv() 397 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_index); in hws_ddr3_tip_init_controller() 506 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt); in hws_ddr3_tip_init_controller() 714 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt); in ddr3_tip_rev2_rank_control() 768 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt); in ddr3_tip_rev3_rank_control() 1174 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt); in adll_calibration() 1320 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_index); in ddr3_tip_freq_set() 1489 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt); in ddr3_tip_freq_set() 1895 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_num); in ddr3_tip_write_cs_result() 2005 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, phy_id); in ddr3_tip_ddr3_reset_phy_regs() [all …]
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| A D | mv_ddr4_mpr_pda_if.c | 266 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, subphy_num); in mv_ddr4_dq_decode() 409 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, subphy_num); in mv_ddr4_dq_pins_mapping() 422 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, subphy_num); in mv_ddr4_dq_pins_mapping()
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| A D | ddr3_training_bist.c | 586 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, subphy); in mv_ddr_dm_vw_get() 600 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, subphy); in mv_ddr_dm_vw_get() 608 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, subphy); in mv_ddr_dm_vw_get()
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| A D | mv_ddr4_training.c | 248 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, i); in mv_ddr4_phy_config() 310 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, i); in mv_ddr4_calibration_adjust()
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| A D | mv_ddr_topology.h | 353 #define VALIDATE_BUS_ACTIVE(mask, id) \ macro
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| A D | mv_ddr4_training_leveling.c | 342 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, subphy_num); in mv_ddr4_dynamic_pb_wl_supp()
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| A D | mv_ddr_plat.c | 714 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, i); in prfa_read() 1536 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, phy_id); in ddr3_tip_configure_phy()
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