Searched refs:WL (Results 1 – 3 of 3) sorted by relevance
| /drivers/ddr/microchip/ |
| A D | ddr2.c | 41 writel(SCL_CSEN | SCL_WCAS_LAT(WL), &ddr2_phy->scl_config_2); in ddr2_phy_init()
150 DIV_ROUND_UP(T_WTR_TCK, 2)) + WL + BL; in ddr2_ctrl_init()
152 wr2prech = DIV_ROUND_UP(T_WR, T_CK_CTRL) + WL + BL; in ddr2_ctrl_init()
167 ((RL - WL + 3) << 28)), &ctrl->dlycfg0); in ddr2_ctrl_init()
195 writel(ODTRDLY(RL - 3) | ODTWDLY(WL - 3) | ODTRLEN(2) | ODTWLEN(3), in ddr2_ctrl_init()
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| A D | ddr2_timing.h | 19 #define WL 4 macro
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| /drivers/ram/renesas/dbsc5/ |
| A D | dram.c | 1423 u32 WL; member
2183 priv->WL = js1[priv->js1_ind].WLsetA; in dbsc5_ddrtbl_calc()
2220 { PI_WRLAT_F2, priv->WL }, in dbsc5_ddrtbl_load()
2229 { PI_WRLAT_ADJ_F2, (priv->WL * 4) + 2 }, in dbsc5_ddrtbl_load()
2586 dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(1), priv->WL); in dbsc5_dbsc_regset()
2627 ((priv->WL + 2 + priv->js2[JS2_tWTR_S]) << 16) | in dbsc5_dbsc_regset()
2628 (priv->WL + 4 + priv->js2[JS2_tWTR_L])); in dbsc5_dbsc_regset()
2645 tmp[0] = (priv->WL * 4) - 1 + 5; in dbsc5_dbsc_regset()
2647 tmp[1] = (priv->WL * 4) - 2 - 2 + 5; in dbsc5_dbsc_regset()
2685 tmp[0] = (priv->WL * 4) - 2; in dbsc5_dbsc_regset()
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