Searched refs:WL_PHY_REG (Results 1 – 10 of 10) sorted by relevance
| /drivers/ddr/marvell/a38x/ |
| A D | mv_ddr4_training_leveling.c | 346 WL_PHY_REG(effective_cs), &rd_data); in mv_ddr4_dynamic_pb_wl_supp()
366 WL_PHY_REG(effective_cs), wr_data); in mv_ddr4_dynamic_pb_wl_supp()
373 WL_PHY_REG(effective_cs), wr_data); in mv_ddr4_dynamic_pb_wl_supp()
381 WL_PHY_REG(effective_cs), wr_data); in mv_ddr4_dynamic_pb_wl_supp()
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| A D | ddr3_training_leveling.c | 968 DDR_PHY_DATA, WL_PHY_REG(0), reg_data); in ddr3_tip_dynamic_write_leveling()
1084 WL_PHY_REG(effective_cs), in ddr3_tip_dynamic_write_leveling()
1299 DDR_PHY_DATA, WL_PHY_REG(effective_cs), &data)); in ddr3_tip_wl_supp_align_phase_shift()
1311 WL_PHY_REG(effective_cs), write_data); in ddr3_tip_wl_supp_align_phase_shift()
1323 WL_PHY_REG(effective_cs), write_data); in ddr3_tip_wl_supp_align_phase_shift()
1335 WL_PHY_REG(effective_cs), write_data); in ddr3_tip_wl_supp_align_phase_shift()
1347 WL_PHY_REG(effective_cs), write_data); in ddr3_tip_wl_supp_align_phase_shift()
1356 WL_PHY_REG(effective_cs), data); in ddr3_tip_wl_supp_align_phase_shift()
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| A D | mv_ddr_regs.h | 448 #define WL_PHY_REG(cs) (WL_PHY_BASE + (cs) * 0x4) macro
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| A D | ddr3_debug.c | 698 WL_PHY_REG(csindex), in ddr3_tip_print_stability_log()
1246 reg = (direction == 0) ? WL_PHY_REG(cs) : RL_PHY_REG(cs); in ddr3_tip_run_leveling_sweep_test()
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| A D | mv_ddr4_training_calibration.c | 1195 DDR_PHY_DATA, WL_PHY_REG(effective_cs), in mv_ddr4_tap_tuning()
1297 WL_PHY_REG(effective_cs), reg_val); in mv_ddr4_tap_tuning()
1593 WL_PHY_REG(effective_cs), reg_val); in mv_ddr4_tap_tuning()
1609 subphy, DDR_PHY_DATA, WL_PHY_REG(effective_cs), in mv_ddr4_tap_tuning()
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| A D | ddr3_training.c | 2010 WL_PHY_REG(effective_cs), in ddr3_tip_ddr3_reset_phy_regs()
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| /drivers/ddr/marvell/a38x/old/ |
| A D | ddr3_training_ip_flow.h | 212 #define WL_PHY_REG 0x0 macro
235 #define PHY_WRITE_DELAY(cs) WL_PHY_REG
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| A D | ddr3_training_leveling.c | 1225 WL_PHY_REG + in ddr3_tip_dynamic_write_leveling()
1569 DDR_PHY_DATA, WL_PHY_REG, &data)); in ddr3_tip_wl_supp_one_clk_err_shift()
1611 bus_id, DDR_PHY_DATA, WL_PHY_REG, in ddr3_tip_wl_supp_align_err_shift()
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| A D | ddr3_debug.c | 569 WL_PHY_REG + in ddr3_tip_print_stability_log()
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| A D | ddr3_training.c | 1891 WL_PHY_REG + in ddr3_tip_ddr3_reset_phy_regs()
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