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Searched refs:WORD_SHIFT (Results 1 – 4 of 4) sorted by relevance

/drivers/ram/k3-ddrss/
A Dlpddr4_am6x.c182 if ((ctlintmap[intr][INT_SHIFT] < WORD_SHIFT) && (ctlintmap[intr][GRP_SHIFT] < WORD_SHIFT)) { in lpddr4_checkctlinterrupt()
201 …_ERROR) && (intr <= LPDDR4_INTR_MR_WRITE_DONE) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) { in lpddr4_ackctlinterrupt_4()
203 } else if ((intr == LPDDR4_INTR_BIST_DONE) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) { in lpddr4_ackctlinterrupt_4()
207 } else if ((intr == LPDDR4_INTR_PARITY_ERROR) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) { in lpddr4_ackctlinterrupt_4()
219 …R_LP_DONE) && (intr <= LPDDR4_INTR_LP_TIMEOUT) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) { in lpddr4_ackctlinterrupt_3()
223 …) && (intr <= LPDDR4_INTR_INIT_POWER_ON_STATE) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) { in lpddr4_ackctlinterrupt_3()
236 …TE_ERROR) && (intr <= LPDDR4_INTR_DFI_TIMEOUT) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) { in lpddr4_ackctlinterrupt_2()
238 …ORE) && (intr <= LPDDR4_INTR_FREQ_DFS_SW_DONE) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) { in lpddr4_ackctlinterrupt_2()
252 if ((result == (u32)0) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) { in lpddr4_ackctlinterrupt()
354 *mmrvalue = (u64)((*mmrvalue << WORD_SHIFT) | lowerdata); in lpddr4_checkmmrreaderror()
A Dlpddr4_j721e.c42 *mask = (u64)((*mask << WORD_SHIFT) | lowermask); in lpddr4_getctlinterruptmask()
67 regval = (u32)((*mask >> WORD_SHIFT) & WORD_MASK); in lpddr4_setctlinterruptmask()
84 if ((u32)intr >= (u32)WORD_SHIFT) { in lpddr4_checkctlinterrupt()
86 fieldshift = (u32)intr - ((u32)WORD_SHIFT); in lpddr4_checkctlinterrupt()
92 if (fieldshift < WORD_SHIFT) { in lpddr4_checkctlinterrupt()
112 if (localinterrupt > WORD_SHIFT) { in lpddr4_ackctlinterrupt()
113 localinterrupt = (localinterrupt - (u32)WORD_SHIFT); in lpddr4_ackctlinterrupt()
270 *mmrvalue = (u64)((*mmrvalue << WORD_SHIFT) | lowerdata); in lpddr4_checkmmrreaderror()
A Dlpddr4.h29 #define WORD_SHIFT (32U) macro
37 #define CTL_INT_MASK_ALL ((u32)LPDDR4_LOR_BITS - WORD_SHIFT)
A Dlpddr4.c461 if ((result == (u32)0) && (ui32irqcount < WORD_SHIFT)) { in lpddr4_setphyindepinterruptmask()
480 if ((result == (u32)0) && ((u32)intr < WORD_SHIFT)) { in lpddr4_checkphyindepinterrupt()
495 if ((result == (u32)0) && ((u32)intr < WORD_SHIFT)) { in lpddr4_ackphyindepinterrupt()

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