| /drivers/reset/ |
| A D | sti-reset.c | 83 #define STIH407_SRST_CORE(_reg, _bit) \ argument
84 _SYSCFG_RST_CH_NO_ACK(stih407_core, _reg, _bit)
86 #define STIH407_SRST_SBC(_reg, _bit) \ argument
87 _SYSCFG_RST_CH_NO_ACK(stih407_sbc_reg, _reg, _bit)
89 #define STIH407_SRST_LPM(_reg, _bit) \ argument
90 _SYSCFG_RST_CH_NO_ACK(stih407_lpm, _reg, _bit)
92 #define STIH407_PDN_0(_bit) \ argument
93 _SYSCFG_RST_CH(stih407_core, SYSCFG_5000, _bit, SYSSTAT_5500, _bit)
94 #define STIH407_PDN_1(_bit) \ argument
95 _SYSCFG_RST_CH(stih407_core, SYSCFG_5001, _bit, SYSSTAT_5501, _bit)
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| A D | reset-uniphier.c | 32 #define UNIPHIER_RESET(_id, _reg, _bit) \ argument
36 .bit = (_bit), \
39 #define UNIPHIER_RESETX(_id, _reg, _bit) \ argument
43 .bit = (_bit), \
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| /drivers/clk/renesas/ |
| A D | rzg2l-cpg.h | 197 #define DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _is_coupled) \ argument
203 .bit = (_bit), \
207 #define DEF_MOD(_name, _id, _parent, _off, _bit) \ argument
208 DEF_MOD_BASE(_name, _id, _parent, _off, _bit, false)
210 #define DEF_COUPLED(_name, _id, _parent, _off, _bit) \ argument
211 DEF_MOD_BASE(_name, _id, _parent, _off, _bit, true)
226 #define DEF_RST_MON(_id, _off, _bit, _monbit) \ argument
229 .bit = (_bit), \
232 #define DEF_RST(_id, _off, _bit) \ argument
233 DEF_RST_MON(_id, _off, _bit, -1)
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| A D | r9a06g032-clocks.c | 45 #define RB(_reg, _bit) ((struct regbit) { \ argument
47 .bit = (_bit) \
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| /drivers/clk/uniphier/ |
| A D | clk-uniphier.h | 59 #define UNIPHIER_CLK_GATE(_id, _parent, _reg, _bit) \ argument
66 .bit = (_bit), \
70 #define UNIPHIER_CLK_GATE_SIMPLE(_id, _reg, _bit) \ argument
71 UNIPHIER_CLK_GATE(_id, UNIPHIER_CLK_ID_INVALID, _reg, _bit)
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| /drivers/clk/meson/ |
| A D | clk_meson.h | 19 #define MESON_GATE(id, _reg, _bit) \ argument
22 .bit = (_bit), \
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| /drivers/pinctrl/nuvoton/ |
| A D | pinctrl-npcm8xx.c | 289 #define FUNC(_name, _reg, _bit, ...) \ argument
295 #define FUNC(_name, _reg, _bit, ...) \ argument
303 #define FUNC(_name, _reg, _bit, ...) { \ argument
309 .bit = _bit, \
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