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Searched refs:_parent (Results 1 – 23 of 23) sorted by relevance

/drivers/clk/renesas/
A Drcar-gen3-cpg.h59 #define DEF_GEN3_SDH(_name, _id, _parent, _offset) \ argument
62 #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ argument
63 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
75 #define DEF_GEN3_OSC(_name, _id, _parent, _div) \ argument
76 DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div)
82 #define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \ argument
93 #define DEF_GEN4_SDH(_name, _id, _parent, _offset) \ argument
96 #define DEF_GEN4_SD(_name, _id, _parent, _offset) \ argument
104 #define DEF_GEN4_OSC(_name, _id, _parent, _div) \ argument
105 DEF_BASE(_name, _id, CLK_TYPE_GEN4_OSC, _parent, .div = _div)
[all …]
A Drzg2l-cpg.h139 #define DEF_BASE(_name, _id, _type, _parent...) \ argument
140 DEF_TYPE(_name, _id, _type, .parent = _parent)
141 #define DEF_SAMPLL(_name, _id, _parent, _conf) \ argument
145 #define DEF_FIXED(_name, _id, _parent, _mult, _div) \ argument
149 .parent = _parent, .dtable = _dtable, \
153 .parent = _parent, .dtable = _dtable, \
169 #define DEF_PLL5_FOUTPOSTDIV(_name, _id, _parent) \ argument
175 #define DEF_DSI_DIV(_name, _id, _parent, _flag) \ argument
201 .parent = (_parent), \
207 #define DEF_MOD(_name, _id, _parent, _off, _bit) \ argument
[all …]
A Drenesas-cpg-mssr.h81 #define DEF_BASE(_name, _id, _type, _parent...) \ argument
82 DEF_TYPE(_name, _id, _type, .parent = _parent)
86 #define DEF_FIXED(_name, _id, _parent, _div, _mult) \ argument
87 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
88 #define DEF_DIV6P1(_name, _id, _parent, _offset) \ argument
89 DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
90 #define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \ argument
91 DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
109 #define DEF_MOD(_name, _mod, _parent...) \ argument
110 { .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent }
/drivers/clk/mediatek/
A Dclk-mt7987.c23 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL)
26 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
29 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
32 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_INFRASYS)
600 #define GATE_INFRA0_INFRA(_id, _name, _parent, _shift) \ argument
602 #define GATE_INFRA0_TOP(_id, _name, _parent, _shift) \ argument
611 #define GATE_INFRA1_INFRA(_id, _name, _parent, _shift) \ argument
613 #define GATE_INFRA1_TOP(_id, _name, _parent, _shift) \ argument
624 #define GATE_INFRA2_TOP(_id, _name, _parent, _shift) \ argument
635 #define GATE_INFRA3_TOP(_id, _name, _parent, _shift) \ argument
[all …]
A Dclk-mt7988.c25 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL)
28 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
31 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
34 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_INFRASYS)
569 #define GATE_INFRA0_INFRA(_id, _name, _parent, _shift) \ argument
571 #define GATE_INFRA0_TOP(_id, _name, _parent, _shift) \ argument
580 #define GATE_INFRA1_INFRA(_id, _name, _parent, _shift) \ argument
582 #define GATE_INFRA1_TOP(_id, _name, _parent, _shift) \ argument
593 #define GATE_INFRA2_TOP(_id, _name, _parent, _shift) \ argument
604 #define GATE_INFRA3_TOP(_id, _name, _parent, _shift) \ argument
[all …]
A Dclk-mt7986.c27 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
30 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
33 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_INFRASYS)
419 .id = _id, .parent = _parent, .regs = &infra_0_cg_regs, \
423 #define GATE_INFRA0_INFRA(_id, _name, _parent, _shift) \ argument
425 #define GATE_INFRA0_TOP(_id, _name, _parent, _shift) \ argument
430 .id = _id, .parent = _parent, .regs = &infra_1_cg_regs, \
434 #define GATE_INFRA1_INFRA(_id, _name, _parent, _shift) \ argument
436 #define GATE_INFRA1_TOP(_id, _name, _parent, _shift) \ argument
445 #define GATE_INFRA2_INFRA(_id, _name, _parent, _shift) \ argument
[all …]
A Dclk-mt7981.c22 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
25 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
28 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_INFRASYS)
413 .id = _id, .parent = _parent, .regs = &infra_0_cg_regs, \
417 #define GATE_INFRA0_INFRA(_id, _name, _parent, _shift) \ argument
419 #define GATE_INFRA0_TOP(_id, _name, _parent, _shift) \ argument
424 .id = _id, .parent = _parent, .regs = &infra_1_cg_regs, \
428 #define GATE_INFRA1_INFRA(_id, _name, _parent, _shift) \ argument
430 #define GATE_INFRA1_TOP(_id, _name, _parent, _shift) \ argument
439 #define GATE_INFRA2_INFRA(_id, _name, _parent, _shift) \ argument
[all …]
A Dclk-mt7622.c77 .parent = _parent, \
88 #define FACTOR0(_id, _parent, _mult, _div) \ argument
91 #define FACTOR1(_id, _parent, _mult, _div) \ argument
95 FACTOR(_id, _parent, _mult, _div, 0)
409 .parent = _parent, \
451 .parent = _parent, \
456 #define GATE_PERI0(_id, _parent, _shift) \ argument
463 .parent = _parent, \
513 .parent = _parent, \
546 .parent = _parent, \
[all …]
A Dclk-mt8512.c62 #define FACTOR0(_id, _parent, _mult, _div) \ argument
65 #define FACTOR1(_id, _parent, _mult, _div) \ argument
69 FACTOR(_id, _parent, _mult, _div, 0)
612 .parent = _parent, \
620 .parent = _parent, \
677 .parent = _parent, \
685 .parent = _parent, \
693 .parent = _parent, \
701 .parent = _parent, \
709 .parent = _parent, \
[all …]
A Dclk-mt7629.c64 #define FACTOR0(_id, _parent, _mult, _div) \ argument
67 #define FACTOR1(_id, _parent, _mult, _div) \ argument
70 #define FACTOR2(_id, _parent, _mult, _div) \ argument
71 FACTOR(_id, _parent, _mult, _div, 0)
428 .parent = _parent, \
457 .parent = _parent, \
465 .parent = _parent, \
502 .parent = _parent, \
508 #define GATE_ETH0(_id, _parent, _shift) \ argument
530 .parent = _parent, \
[all …]
A Dclk-mt8365.c512 .parent = _parent, \
520 .parent = _parent, \
528 .parent = _parent, \
590 .parent = _parent, \
596 #define GATE_IFR2(_id, _parent, _shift) \ argument
597 GATE_IFRX(_id, _parent, _shift, &ifr2_cg_regs)
599 #define GATE_IFR3(_id, _parent, _shift) \ argument
600 GATE_IFRX(_id, _parent, _shift, &ifr3_cg_regs)
602 #define GATE_IFR4(_id, _parent, _shift) \ argument
605 #define GATE_IFR5(_id, _parent, _shift) \ argument
[all …]
A Dclk-mt8516.c52 #define FACTOR0(_id, _parent, _mult, _div) \ argument
55 #define FACTOR1(_id, _parent, _mult, _div) \ argument
58 #define FACTOR2(_id, _parent, _mult, _div) \ argument
59 FACTOR(_id, _parent, _mult, _div, 0)
579 .parent = _parent, \
587 .parent = _parent, \
595 .parent = _parent, \
603 .parent = _parent, \
611 .parent = _parent, \
619 .parent = _parent, \
[all …]
A Dclk-mt7623.c260 #define FACTOR0(_id, _parent, _mult, _div) \ argument
263 #define FACTOR1(_id, _parent, _mult, _div) \ argument
266 #define FACTOR2(_id, _parent, _mult, _div) \ argument
267 FACTOR(_id, _parent, _mult, _div, 0)
777 .parent = _parent, \
782 #define GATE_INFRA(_id, _parent, _shift) \ argument
892 .parent = _parent, \
897 #define GATE_PERI0(_id, _parent, _shift) \ argument
902 #define GATE_PERI1(_id, _parent, _shift) { \ argument
904 .parent = _parent, \
[all …]
A Dclk-mt8518.c61 FACTOR(_id, _parent, _mult, _div, 0)
1302 .parent = _parent, \
1310 .parent = _parent, \
1318 .parent = _parent, \
1326 .parent = _parent, \
1334 .parent = _parent, \
1342 .parent = _parent, \
1350 .parent = _parent, \
1358 .parent = _parent, \
1366 .parent = _parent, \
[all …]
A Dclk-mtk.h83 #define FIXED_CLK(_id, _parent, _rate) { \ argument
85 .parent = _parent, \
106 #define FACTOR(_id, _parent, _mult, _div, _flags) { \ argument
108 .parent = _parent, \
A Dclk-mt8183.c628 #define GATE_INFRA0(_id, _parent, _shift) { \ argument
630 .parent = _parent, \
636 #define GATE_INFRA1(_id, _parent, _shift) { \ argument
638 .parent = _parent, \
644 #define GATE_INFRA2(_id, _parent, _shift) { \ argument
646 .parent = _parent, \
652 #define GATE_INFRA3(_id, _parent, _shift) { \ argument
654 .parent = _parent, \
/drivers/clk/sophgo/
A Dclk-ip.h101 #define CV1800B_GATE(_id, _name, _parent, \ argument
110 .parent_name = _parent, \
114 #define CV1800B_DIV(_id, _name, _parent, \ argument
124 .parent_name = _parent, \
131 #define CV1800B_BYPASS_DIV(_id, _name, _parent, \ argument
138 .div = CV1800B_DIV(_id, _name, _parent, \
146 #define CV1800B_FIXED_DIV(_id, _name, _parent, \ argument
155 .parent_name = _parent, \
166 .div = CV1800B_FIXED_DIV(_id, _name, _parent, \
249 #define CV1800B_AUDIO(_id, _name, _parent, \ argument
[all …]
/drivers/clk/stm32/
A Dclk-stm32-core.h225 #define STM32_GATE(_id, _name, _parent, _flags, _gate_id, _sec_id) \ argument
230 .parent_name = _parent, \
259 #define STM32_COMPOSITE_NOMUX(_id, _name, _parent, _flags, _sec_id, \ argument
264 .parent_name = _parent, \
A Dclk-stm32mp13.c594 #define PCLK(_id, _name, _parent, _flags, _gate_id, _sec_id) \ argument
595 STM32_GATE(_id, _name, _parent, _flags, _gate_id, _sec_id)
597 #define TIMER(_id, _name, _parent, _flags, _gate_id, _sec_id) \ argument
598 STM32_GATE(_id, _name, _parent, ((_flags) | CLK_SET_RATE_PARENT), \
/drivers/clk/uniphier/
A Dclk-uniphier.h59 #define UNIPHIER_CLK_GATE(_id, _parent, _reg, _bit) \ argument
64 .parent_id = (_parent), \
/drivers/clk/meson/
A Da1.c118 #define CLK_DIV(_name, _reg, _shift, _width, _parent) \ argument
120 .parents = (const unsigned int[]) { (_parent) }, \
131 #define CLK_DIV_FIXED(_name, _div, _parent) \ argument
133 .parents = (const unsigned int[]) { (_parent) }, \
148 #define CLK_GATE(_name, _reg, _shift, _parent) \ argument
150 .parents = (const unsigned int[]) { (_parent) }, \
161 #define CLK_PLL(_name, _parent, ...) \ argument
164 .parents = (const unsigned int[]) { (_parent) }, \
/drivers/clk/
A Dclk_k210.c334 #define CLK(id, _name, _parent, _div, _gate) \ argument
337 .parent = (_parent), \
349 #define CLK_PLL(id, _pll, _parent) \ argument
353 .parent = (_parent), \
/drivers/clk/thead/
A Dclk-th1520-ap.c86 #define CCU_GATE(_clkid, _struct, _name, _parent, _reg, _gate, _flags) \ argument
88 .parent = _parent, \

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