| /drivers/clk/mediatek/ |
| A D | clk-mtk.h | 171 .mux_mask = BIT(_width) - 1, \
179 #define MUX_GATE(_id, _parents, _reg, _shift, _width, _gate) \ argument
180 MUX_GATE_FLAGS(_id, _parents, _reg, _shift, _width, _gate, 0)
186 .mux_mask = BIT(_width) - 1, \
192 #define MUX_MIXED(_id, _parents, _reg, _shift, _width) \ argument
193 MUX_MIXED_FLAGS(_id, _parents, _reg, _shift, _width, 0)
199 .mux_mask = BIT(_width) - 1, \
205 #define MUX(_id, _parents, _reg, _shift, _width) \ argument
206 MUX_FLAGS(_id, _parents, _reg, _shift, _width, 0)
209 _mux_clr_ofs, _shift, _width, _gate, \ argument
[all …]
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| A D | clk-mt7986.c | 228 _shift, _width, _gate, _upd_ofs, _upd) \ argument
233 .mux_mask = BIT(_width) - 1, .gate_reg = _mux_ofs, \
364 #define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \ argument
368 .mux_shift = _shift, .mux_mask = BIT(_width) - 1, \
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| A D | clk-mt7981.c | 232 _shift, _width, _gate, _upd_ofs, _upd) \ argument
237 .mux_mask = BIT(_width) - 1, .gate_reg = _mux_ofs, \
357 #define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \ argument
361 .mux_shift = _shift, .mux_mask = BIT(_width) - 1, \
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| A D | clk-mt7987.c | 333 _shift, _width, _gate, _upd_ofs, _upd) \ argument
338 .mux_shift = (_shift), .mux_mask = BIT(_width) - 1, \
538 #define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \ argument
542 .mux_shift = (_shift), .mux_mask = BIT(_width) - 1, \
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| A D | clk-mt7988.c | 277 _shift, _width, _gate, _upd_ofs, _upd) \ argument
282 .mux_mask = BIT(_width) - 1, .gate_reg = _mux_ofs, \
483 #define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \ argument
487 .mux_mask = BIT(_width) - 1, .parent = _parents, \
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| A D | clk-mt7622.c | 430 #define PERI_MUX(_id, _parents, _reg, _shift, _width) \ argument
431 MUX_FLAGS(_id, _parents, _reg, _shift, _width, CLK_PARENT_TOPCKGEN)
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| /drivers/clk/sophgo/ |
| A D | clk-common.h | 34 #define CV1800B_CLK_REGFIELD(_offset, _shift, _width) \ argument
38 .width = _width, \
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| /drivers/clk/microchip/ |
| A D | mpfs_clk_msspll.c | 76 #define CLK_PLL(_id, _name, _shift, _width, _reg_offset, _flags) { \ argument
80 .width = _width, \
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| A D | mpfs_clk_cfg.c | 104 #define CLK_CFG(_id, _name, _shift, _width, _table, _flags) { \ argument
108 .cfg.width = _width, \
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| /drivers/clk/meson/ |
| A D | a1.c | 105 #define CLK_MUX(_name, _reg, _shift, _width, ...) \ argument
111 .width = (_width), \
118 #define CLK_DIV(_name, _reg, _shift, _width, _parent) \ argument
124 .width = (_width), \
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| /drivers/clk/ |
| A D | clk_k210.c | 121 #define DIV(id, _off, _shift, _width, _type) \ argument
126 .width = (_width), \
251 #define MUX_PARENTS(id, _off, _shift, _width, ...) \ argument
257 .width = (_width), \
279 #define PLL(_off, _shift, _width) { \ argument
282 .width = (_width), \
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| /drivers/clk/thead/ |
| A D | clk-th1520-ap.c | 73 #define TH_CCU_ARG(_shift, _width) \ argument
76 .width = _width, \
79 #define TH_CCU_DIV_FLAGS(_shift, _width, _flags) \ argument
82 .width = _width, \
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| /drivers/clk/stm32/ |
| A D | clk-stm32mp13.c | 449 #define DIV_CFG(id, _offset, _shift, _width, _flags, _table) \ argument
453 .width = _width, \
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