1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright 2008-2014 Freescale Semiconductor, Inc.
4 * Copyright 2021 NXP
5 */
6
7 #include <config.h>
8 #ifdef CONFIG_PPC
9 #include <asm/fsl_law.h>
10 #include <asm/ppc.h>
11 #endif
12 #include <div64.h>
13 #include <linux/delay.h>
14
15 #include <fsl_ddr.h>
16 #include <fsl_immap.h>
17 #include <log.h>
18 #include <asm/io.h>
19 #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
20 defined(CONFIG_ARM)
21 #include <asm/arch/clock.h>
22 #endif
23
24 /* To avoid 64-bit full-divides, we factor this here */
25 #define ULL_2E12 2000000000000ULL
26 #define UL_5POW12 244140625UL
27 #define UL_2POW13 (1UL << 13)
28
29 #define ULL_8FS 0xFFFFFFFFULL
30
fsl_ddr_get_version(unsigned int ctrl_num)31 u32 fsl_ddr_get_version(unsigned int ctrl_num)
32 {
33 struct ccsr_ddr __iomem *ddr;
34 u32 ver_major_minor_errata;
35
36 switch (ctrl_num) {
37 case 0:
38 ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
39 break;
40 #if defined(CFG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
41 case 1:
42 ddr = (void *)CFG_SYS_FSL_DDR2_ADDR;
43 break;
44 #endif
45 #if defined(CFG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
46 case 2:
47 ddr = (void *)CFG_SYS_FSL_DDR3_ADDR;
48 break;
49 #endif
50 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
51 case 3:
52 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
53 break;
54 #endif
55 default:
56 printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
57 return 0;
58 }
59 ver_major_minor_errata = (ddr_in32(&ddr->ip_rev1) & 0xFFFF) << 8;
60 ver_major_minor_errata |= (ddr_in32(&ddr->ip_rev2) & 0xFF00) >> 8;
61
62 return ver_major_minor_errata;
63 }
64
65 /*
66 * Round up mclk_ps to nearest 1 ps in memory controller code
67 * if the error is 0.5ps or more.
68 *
69 * If an imprecise data rate is too high due to rounding error
70 * propagation, compute a suitably rounded mclk_ps to compute
71 * a working memory controller configuration.
72 */
get_memory_clk_period_ps(const unsigned int ctrl_num)73 unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num)
74 {
75 unsigned int data_rate = get_ddr_freq(ctrl_num);
76 unsigned int result;
77
78 /* Round to nearest 10ps, being careful about 64-bit multiply/divide */
79 unsigned long long rem, mclk_ps = ULL_2E12;
80 if (data_rate) {
81 /* Now perform the big divide, the result fits in 32-bits */
82 rem = do_div(mclk_ps, data_rate);
83 result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps;
84 } else {
85 result = 0;
86 }
87
88 return result;
89 }
90
91 /* Convert picoseconds into DRAM clock cycles (rounding up if needed). */
picos_to_mclk(const unsigned int ctrl_num,unsigned int picos)92 unsigned int picos_to_mclk(const unsigned int ctrl_num, unsigned int picos)
93 {
94 unsigned long long clks, clks_rem;
95 unsigned long data_rate = get_ddr_freq(ctrl_num);
96
97 /* Short circuit for zero picos */
98 if (!picos)
99 return 0;
100
101 /* First multiply the time by the data rate (32x32 => 64) */
102 clks = picos * (unsigned long long)data_rate;
103 /*
104 * Now divide by 5^12 and track the 32-bit remainder, then divide
105 * by 2*(2^12) using shifts (and updating the remainder).
106 */
107 clks_rem = do_div(clks, UL_5POW12);
108 clks_rem += (clks & (UL_2POW13-1)) * UL_5POW12;
109 clks >>= 13;
110
111 /* If we had a remainder greater than the 1ps error, then round up */
112 if (clks_rem > data_rate)
113 clks++;
114
115 /* Clamp to the maximum representable value */
116 if (clks > ULL_8FS)
117 clks = ULL_8FS;
118 return (unsigned int) clks;
119 }
120
mclk_to_picos(const unsigned int ctrl_num,unsigned int mclk)121 unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk)
122 {
123 return get_memory_clk_period_ps(ctrl_num) * mclk;
124 }
125
126 #ifdef CONFIG_PPC
127 void
__fsl_ddr_set_lawbar(const common_timing_params_t * memctl_common_params,unsigned int law_memctl,unsigned int ctrl_num)128 __fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
129 unsigned int law_memctl,
130 unsigned int ctrl_num)
131 {
132 unsigned long long base = memctl_common_params->base_address;
133 unsigned long long size = memctl_common_params->total_mem;
134
135 /*
136 * If no DIMMs on this controller, do not proceed any further.
137 */
138 if (!memctl_common_params->ndimms_present) {
139 return;
140 }
141
142 #if !defined(CONFIG_PHYS_64BIT)
143 if (base >= CFG_MAX_MEM_MAPPED)
144 return;
145 if ((base + size) >= CFG_MAX_MEM_MAPPED)
146 size = CFG_MAX_MEM_MAPPED - base;
147 #endif
148 if (set_ddr_laws(base, size, law_memctl) < 0) {
149 printf("%s: ERROR (ctrl #%d, TRGT ID=%x)\n", __func__, ctrl_num,
150 law_memctl);
151 return;
152 }
153 debug("setup ddr law base = 0x%llx, size 0x%llx, TRGT_ID 0x%x\n",
154 base, size, law_memctl);
155 }
156
157 __attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void
158 fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
159 unsigned int memctl_interleaved,
160 unsigned int ctrl_num);
161 #endif
162
fsl_ddr_set_intl3r(const unsigned int granule_size)163 void fsl_ddr_set_intl3r(const unsigned int granule_size)
164 {
165 #ifdef CONFIG_E6500
166 u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
167 *mcintl3r = 0x80000000 | (granule_size & 0x1f);
168 debug("Enable MCINTL3R with granule size 0x%x\n", granule_size);
169 #endif
170 }
171
fsl_ddr_get_intl3r(void)172 u32 fsl_ddr_get_intl3r(void)
173 {
174 u32 val = 0;
175 #ifdef CONFIG_E6500
176 u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
177 val = *mcintl3r;
178 #endif
179 return val;
180 }
181
print_ddr_info(unsigned int start_ctrl)182 void print_ddr_info(unsigned int start_ctrl)
183 {
184 struct ccsr_ddr __iomem *ddr =
185 (struct ccsr_ddr __iomem *)(CFG_SYS_FSL_DDR_ADDR);
186
187 #if defined(CONFIG_E6500) && (CONFIG_SYS_NUM_DDR_CTLRS == 3)
188 u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
189 #endif
190 #if (CONFIG_SYS_NUM_DDR_CTLRS > 1)
191 uint32_t cs0_config = ddr_in32(&ddr->cs0_config);
192 #endif
193 uint32_t sdram_cfg = ddr_in32(&ddr->sdram_cfg);
194 int cas_lat;
195
196 #if CONFIG_SYS_NUM_DDR_CTLRS >= 2
197 if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) ||
198 (start_ctrl == 1)) {
199 ddr = (void __iomem *)CFG_SYS_FSL_DDR2_ADDR;
200 sdram_cfg = ddr_in32(&ddr->sdram_cfg);
201 }
202 #endif
203 #if CONFIG_SYS_NUM_DDR_CTLRS >= 3
204 if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) ||
205 (start_ctrl == 2)) {
206 ddr = (void __iomem *)CFG_SYS_FSL_DDR3_ADDR;
207 sdram_cfg = ddr_in32(&ddr->sdram_cfg);
208 }
209 #endif
210
211 if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
212 puts(" (DDR not enabled)\n");
213 return;
214 }
215
216 puts(" (DDR");
217 switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
218 SDRAM_CFG_SDRAM_TYPE_SHIFT) {
219 case SDRAM_TYPE_DDR1:
220 puts("1");
221 break;
222 case SDRAM_TYPE_DDR2:
223 puts("2");
224 break;
225 case SDRAM_TYPE_DDR3:
226 puts("3");
227 break;
228 case SDRAM_TYPE_DDR4:
229 puts("4");
230 break;
231 default:
232 puts("?");
233 break;
234 }
235
236 if (sdram_cfg & SDRAM_CFG_32_BE)
237 puts(", 32-bit");
238 else if (sdram_cfg & SDRAM_CFG_16_BE)
239 puts(", 16-bit");
240 else
241 puts(", 64-bit");
242
243 /* Calculate CAS latency based on timing cfg values */
244 cas_lat = ((ddr_in32(&ddr->timing_cfg_1) >> 16) & 0xf);
245 if (fsl_ddr_get_version(0) <= 0x40400)
246 cas_lat += 1;
247 else
248 cas_lat += 2;
249 cas_lat += ((ddr_in32(&ddr->timing_cfg_3) >> 12) & 3) << 4;
250 printf(", CL=%d", cas_lat >> 1);
251 if (cas_lat & 0x1)
252 puts(".5");
253
254 if (sdram_cfg & SDRAM_CFG_ECC_EN)
255 puts(", ECC on)");
256 else
257 puts(", ECC off)");
258
259 #if (CONFIG_SYS_NUM_DDR_CTLRS == 3)
260 #ifdef CONFIG_E6500
261 if (*mcintl3r & 0x80000000) {
262 puts("\n");
263 puts(" DDR Controller Interleaving Mode: ");
264 switch (*mcintl3r & 0x1f) {
265 case FSL_DDR_3WAY_1KB_INTERLEAVING:
266 puts("3-way 1KB");
267 break;
268 case FSL_DDR_3WAY_4KB_INTERLEAVING:
269 puts("3-way 4KB");
270 break;
271 case FSL_DDR_3WAY_8KB_INTERLEAVING:
272 puts("3-way 8KB");
273 break;
274 default:
275 puts("3-way UNKNOWN");
276 break;
277 }
278 }
279 #endif
280 #endif
281 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
282 if ((cs0_config & 0x20000000) && (start_ctrl == 0)) {
283 puts("\n");
284 puts(" DDR Controller Interleaving Mode: ");
285
286 switch ((cs0_config >> 24) & 0xf) {
287 case FSL_DDR_256B_INTERLEAVING:
288 puts("256B");
289 break;
290 case FSL_DDR_CACHE_LINE_INTERLEAVING:
291 puts("cache line");
292 break;
293 case FSL_DDR_PAGE_INTERLEAVING:
294 puts("page");
295 break;
296 case FSL_DDR_BANK_INTERLEAVING:
297 puts("bank");
298 break;
299 case FSL_DDR_SUPERBANK_INTERLEAVING:
300 puts("super-bank");
301 break;
302 default:
303 puts("invalid");
304 break;
305 }
306 }
307 #endif
308
309 if ((sdram_cfg >> 8) & 0x7f) {
310 puts("\n");
311 puts(" DDR Chip-Select Interleaving Mode: ");
312 switch(sdram_cfg >> 8 & 0x7f) {
313 case FSL_DDR_CS0_CS1_CS2_CS3:
314 puts("CS0+CS1+CS2+CS3");
315 break;
316 case FSL_DDR_CS0_CS1:
317 puts("CS0+CS1");
318 break;
319 case FSL_DDR_CS2_CS3:
320 puts("CS2+CS3");
321 break;
322 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
323 puts("CS0+CS1 and CS2+CS3");
324 break;
325 default:
326 puts("invalid");
327 break;
328 }
329 }
330 }
331
detail_board_ddr_info(void)332 void __weak detail_board_ddr_info(void)
333 {
334 print_ddr_info(0);
335 }
336
board_add_ram_info(int use_default)337 void board_add_ram_info(int use_default)
338 {
339 detail_board_ddr_info();
340 }
341
342 #ifdef CONFIG_FSL_DDR_SYNC_REFRESH
343 #define DDRC_DEBUG20_INIT_DONE 0x80000000
344 #define DDRC_DEBUG2_RF 0x00000040
fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,unsigned int last_ctrl)345 void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,
346 unsigned int last_ctrl)
347 {
348 unsigned int i;
349 u32 ddrc_debug20;
350 u32 ddrc_debug2[CONFIG_SYS_NUM_DDR_CTLRS] = {};
351 u32 *ddrc_debug2_p[CONFIG_SYS_NUM_DDR_CTLRS] = {};
352 struct ccsr_ddr __iomem *ddr;
353
354 for (i = first_ctrl; i <= last_ctrl; i++) {
355 switch (i) {
356 case 0:
357 ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
358 break;
359 #if defined(CFG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
360 case 1:
361 ddr = (void *)CFG_SYS_FSL_DDR2_ADDR;
362 break;
363 #endif
364 #if defined(CFG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
365 case 2:
366 ddr = (void *)CFG_SYS_FSL_DDR3_ADDR;
367 break;
368 #endif
369 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
370 case 3:
371 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
372 break;
373 #endif
374 default:
375 printf("%s unexpected ctrl = %u\n", __func__, i);
376 return;
377 }
378 ddrc_debug20 = ddr_in32(&ddr->debug[19]);
379 ddrc_debug2_p[i] = &ddr->debug[1];
380 while (!(ddrc_debug20 & DDRC_DEBUG20_INIT_DONE)) {
381 /* keep polling until DDRC init is done */
382 udelay(100);
383 ddrc_debug20 = ddr_in32(&ddr->debug[19]);
384 }
385 ddrc_debug2[i] = ddr_in32(&ddr->debug[1]) | DDRC_DEBUG2_RF;
386 }
387 /*
388 * Sync refresh
389 * This is put together to make sure the refresh reqeusts are sent
390 * closely to each other.
391 */
392 for (i = first_ctrl; i <= last_ctrl; i++)
393 ddr_out32(ddrc_debug2_p[i], ddrc_debug2[i]);
394 }
395 #endif /* CONFIG_FSL_DDR_SYNC_REFRESH */
396
remove_unused_controllers(fsl_ddr_info_t * info)397 void remove_unused_controllers(fsl_ddr_info_t *info)
398 {
399 #ifdef CONFIG_SYS_FSL_HAS_CCN504
400 int i;
401 u64 nodeid;
402 void *hnf_sam_ctrl = (void *)(CCI_HN_F_0_BASE + CCN_HN_F_SAM_CTL);
403 bool ddr0_used = false;
404 bool ddr1_used = false;
405
406 for (i = 0; i < 8; i++) {
407 nodeid = in_le64(hnf_sam_ctrl) & CCN_HN_F_SAM_NODEID_MASK;
408 if (nodeid == CCN_HN_F_SAM_NODEID_DDR0) {
409 ddr0_used = true;
410 } else if (nodeid == CCN_HN_F_SAM_NODEID_DDR1) {
411 ddr1_used = true;
412 } else {
413 printf("Unknown nodeid in HN-F SAM control: 0x%llx\n",
414 nodeid);
415 }
416 hnf_sam_ctrl += (CCI_HN_F_1_BASE - CCI_HN_F_0_BASE);
417 }
418 if (!ddr0_used && !ddr1_used) {
419 printf("Invalid configuration in HN-F SAM control\n");
420 return;
421 }
422
423 if (!ddr0_used && info->first_ctrl == 0) {
424 info->first_ctrl = 1;
425 info->num_ctrls = 1;
426 debug("First DDR controller disabled\n");
427 return;
428 }
429
430 if (!ddr1_used && info->first_ctrl + info->num_ctrls > 1) {
431 info->num_ctrls = 1;
432 debug("Second DDR controller disabled\n");
433 }
434 #endif
435 }
436