1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2019 Andes Technology Corporation
4 * Rick Chen, Andes Technology Corporation <rick@andestech.com>
5 */
6
7 #include <command.h>
8 #include <cache.h>
9 #include <dm.h>
10 #include <hang.h>
11 #include <asm/global_data.h>
12 #include <asm/io.h>
13 #include <dm/ofnode.h>
14 #include <linux/bitops.h>
15
16 struct l2cache {
17 volatile u64 configure;
18 volatile u64 control;
19 volatile u64 hpm0;
20 volatile u64 hpm1;
21 volatile u64 hpm2;
22 volatile u64 hpm3;
23 volatile u64 error_status;
24 volatile u64 ecc_error;
25 volatile u64 cctl_command0;
26 volatile u64 cctl_access_line0;
27 volatile u64 cctl_command1;
28 volatile u64 cctl_access_line1;
29 volatile u64 cctl_command2;
30 volatile u64 cctl_access_line2;
31 volatile u64 cctl_command3;
32 volatile u64 cctl_access_line3;
33 volatile u64 cctl_status;
34 };
35
36 /* Configuration register */
37 #define MEM_MAP_OFF 20
38 #define MEM_MAP_MSK BIT(MEM_MAP_OFF)
39 /* offset of v0 memory map (Gen1) */
40 static u32 cmd_stride = 0x10;
41 static u32 status_stride = 0x0;
42 static u32 status_bit_offset = 0x4;
43
44 /* Control Register */
45 #define L2_ENABLE 0x1
46 /* prefetch */
47 #define IPREPETCH_OFF 3
48 #define DPREPETCH_OFF 5
49 #define IPREPETCH_MSK (3 << IPREPETCH_OFF)
50 #define DPREPETCH_MSK (3 << DPREPETCH_OFF)
51 /* tag ram */
52 #define TRAMOCTL_OFF 8
53 #define TRAMICTL_OFF 10
54 #define TRAMOCTL_MSK (3 << TRAMOCTL_OFF)
55 #define TRAMICTL_MSK BIT(TRAMICTL_OFF)
56 /* data ram */
57 #define DRAMOCTL_OFF 11
58 #define DRAMICTL_OFF 13
59 #define DRAMOCTL_MSK (3 << DRAMOCTL_OFF)
60 #define DRAMICTL_MSK BIT(DRAMICTL_OFF)
61
62 /* CCTL Command Register */
63 #define CCTL_CMD_REG(base, hart) ((ulong)(base) + 0x40 + (hart) * (cmd_stride))
64 #define L2_WBINVAL_ALL 0x12
65
66 /* CCTL Status Register */
67 #define CCTL_STATUS_REG(base, hart) ((ulong)(base) + 0x80 + (hart) * (status_stride))
68 #define CCTL_STATUS_MSK(hart) (0xf << ((hart) * (status_bit_offset)))
69 #define CCTL_STATUS_IDLE(hart) (0 << ((hart) * (status_bit_offset)))
70 #define CCTL_STATUS_PROCESS(hart) (1 << ((hart) * (status_bit_offset)))
71 #define CCTL_STATUS_ILLEGAL(hart) (2 << ((hart) * (status_bit_offset)))
72
73 DECLARE_GLOBAL_DATA_PTR;
74
75 struct andes_l2_plat {
76 struct l2cache *regs;
77 u32 iprefetch;
78 u32 dprefetch;
79 u32 tram_ctl[2];
80 u32 dram_ctl[2];
81 };
82
andes_l2_enable(struct udevice * dev)83 static int andes_l2_enable(struct udevice *dev)
84 {
85 struct andes_l2_plat *plat = dev_get_plat(dev);
86 volatile struct l2cache *regs = plat->regs;
87
88 if (regs)
89 setbits_le32(®s->control, L2_ENABLE);
90
91 return 0;
92 }
93
andes_l2_disable(struct udevice * dev)94 static int andes_l2_disable(struct udevice *dev)
95 {
96 struct andes_l2_plat *plat = dev_get_plat(dev);
97 volatile struct l2cache *regs = plat->regs;
98 u8 hart = gd->arch.boot_hart;
99
100 void __iomem *cctlcmd = (void __iomem *)CCTL_CMD_REG(regs, hart);
101 void __iomem *cctlstatus = (void __iomem *)CCTL_STATUS_REG(regs, hart);
102
103 if ((regs) && (readl(®s->control) & L2_ENABLE)) {
104 writel(L2_WBINVAL_ALL, cctlcmd);
105
106 while ((readl(cctlstatus) & CCTL_STATUS_MSK(hart))) {
107 if ((readl(cctlstatus) & CCTL_STATUS_ILLEGAL(hart))) {
108 printf("L2 flush illegal! hanging...");
109 hang();
110 }
111 }
112 clrbits_le32(®s->control, L2_ENABLE);
113 }
114
115 return 0;
116 }
117
andes_l2_of_to_plat(struct udevice * dev)118 static int andes_l2_of_to_plat(struct udevice *dev)
119 {
120 struct andes_l2_plat *plat = dev_get_plat(dev);
121 struct l2cache *regs;
122
123 regs = dev_read_addr_ptr(dev);
124 plat->regs = regs;
125
126 plat->iprefetch = -EINVAL;
127 plat->dprefetch = -EINVAL;
128 plat->tram_ctl[0] = -EINVAL;
129 plat->dram_ctl[0] = -EINVAL;
130
131 /* Instruction and data fetch prefetch depth */
132 dev_read_u32(dev, "andes,inst-prefetch", &plat->iprefetch);
133 dev_read_u32(dev, "andes,data-prefetch", &plat->dprefetch);
134
135 /* Set tag RAM and data RAM setup and output cycle */
136 dev_read_u32_array(dev, "andes,tag-ram-ctl", plat->tram_ctl, 2);
137 dev_read_u32_array(dev, "andes,data-ram-ctl", plat->dram_ctl, 2);
138
139 return 0;
140 }
141
andes_l2_probe(struct udevice * dev)142 static int andes_l2_probe(struct udevice *dev)
143 {
144 struct andes_l2_plat *plat = dev_get_plat(dev);
145 struct l2cache *regs = plat->regs;
146 u32 cfg_val, ctl_val;
147
148 cfg_val = readl(®s->configure);
149 ctl_val = readl(®s->control);
150
151 /* If true, v1 memory map (Gen2) */
152 if (cfg_val & MEM_MAP_MSK) {
153 cmd_stride = 0x1000;
154 status_stride = 0x1000;
155 status_bit_offset = 0x0;
156 }
157
158 ctl_val |= L2_ENABLE;
159
160 if (plat->iprefetch != -EINVAL) {
161 ctl_val &= ~(IPREPETCH_MSK);
162 ctl_val |= (plat->iprefetch << IPREPETCH_OFF);
163 }
164
165 if (plat->dprefetch != -EINVAL) {
166 ctl_val &= ~(DPREPETCH_MSK);
167 ctl_val |= (plat->dprefetch << DPREPETCH_OFF);
168 }
169
170 if (plat->tram_ctl[0] != -EINVAL) {
171 ctl_val &= ~(TRAMOCTL_MSK | TRAMICTL_MSK);
172 ctl_val |= plat->tram_ctl[0] << TRAMOCTL_OFF;
173 ctl_val |= plat->tram_ctl[1] << TRAMICTL_OFF;
174 }
175
176 if (plat->dram_ctl[0] != -EINVAL) {
177 ctl_val &= ~(DRAMOCTL_MSK | DRAMICTL_MSK);
178 ctl_val |= plat->dram_ctl[0] << DRAMOCTL_OFF;
179 ctl_val |= plat->dram_ctl[1] << DRAMICTL_OFF;
180 }
181
182 writel(ctl_val, ®s->control);
183
184 return 0;
185 }
186
187 static const struct udevice_id andes_l2_cache_ids[] = {
188 { .compatible = "cache" },
189 {}
190 };
191
192 static const struct cache_ops andes_l2_cache_ops = {
193 .enable = andes_l2_enable,
194 .disable = andes_l2_disable,
195 };
196
197 U_BOOT_DRIVER(andes_l2_cache) = {
198 .name = "andes_l2_cache",
199 .id = UCLASS_CACHE,
200 .of_match = andes_l2_cache_ids,
201 .of_to_plat = andes_l2_of_to_plat,
202 .probe = andes_l2_probe,
203 .plat_auto = sizeof(struct andes_l2_plat),
204 .ops = &andes_l2_cache_ops,
205 .flags = DM_FLAG_PRE_RELOC,
206 };
207