Searched refs:clk_ctrl (Results 1 – 3 of 3) sorted by relevance
| /drivers/clk/ |
| A D | clk_zynq.c | 156 u32 clk_ctrl, srcsel; in zynq_clk_get_gem_rclk() local
173 u32 clk_621, clk_ctrl, div; in zynq_clk_get_cpu_rate() local
205 u32 clk_ctrl, div; in zynq_clk_get_ddr2x_rate() local
217 u32 clk_ctrl, div; in zynq_clk_get_ddr3x_rate() local
229 u32 clk_ctrl, div0, div1; in zynq_clk_get_dci_rate() local
245 u32 clk_ctrl, div0; in zynq_clk_get_peripheral_rate() local
320 u32 clk_ctrl, div0 = 0, div1 = 0; in zynq_clk_set_peripheral_rate() local
325 clk_ctrl = readl(reg); in zynq_clk_set_peripheral_rate()
329 clk_ctrl &= ~CLK_CTRL_DIV0_MASK; in zynq_clk_set_peripheral_rate()
331 clk_ctrl &= ~CLK_CTRL_DIV1_MASK; in zynq_clk_set_peripheral_rate()
[all …]
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| A D | clk_zynqmp.c | 378 u32 clk_ctrl, reset, mul; in zynqmp_clk_get_pll_rate() local
388 if (clk_ctrl & PLLCTRL_BYPASS_MASK) in zynqmp_clk_get_pll_rate()
401 if (clk_ctrl & (1 << 16)) in zynqmp_clk_get_pll_rate()
426 u32 clk_ctrl, div, srcsel; in zynqmp_clk_get_cpu_rate() local
450 u32 clk_ctrl, div, srcsel; in zynqmp_clk_get_ddr_rate() local
474 u32 clk_ctrl, srcsel; in zynqmp_clk_get_dll_rate() local
498 u32 clk_ctrl, div0, srcsel; in zynqmp_clk_get_peripheral_rate() local
538 u32 clk_ctrl, div0, srcsel; in zynqmp_clk_get_crf_crl_rate() local
645 u32 clk_ctrl, div0 = 0, div1 = 0; in zynqmp_clk_set_peripheral_rate() local
664 clk_ctrl &= ~CLK_CTRL_DIV0_MASK; in zynqmp_clk_set_peripheral_rate()
[all …]
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| /drivers/spi/ |
| A D | ti_qspi.c | 82 u32 clk_ctrl; member
128 writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN, in ti_qspi_set_speed()
129 &priv->base->clk_ctrl); in ti_qspi_set_speed()
131 writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl); in ti_qspi_set_speed()
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