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Searched refs:clk_div (Results 1 – 20 of 20) sorted by relevance

/drivers/mmc/
A Dca_dw_mmc.c76 u8 clk_div; in ca_dwmci_get_mmc_clock() local
80 clk_div = 4; in ca_dwmci_get_mmc_clock()
83 clk_div = 2; in ca_dwmci_get_mmc_clock()
86 clk_div = 1; in ca_dwmci_get_mmc_clock()
89 return SD_SCLK_MAX / clk_div; in ca_dwmci_get_mmc_clock()
A Dexynos_dw_mmc.c166 u8 clk_div; in exynos_dwmci_get_clk() local
173 clk_div = exynos_dwmmc_get_ciu_div(host); in exynos_dwmci_get_clk()
174 err = exynos_dwmmc_set_sclk(host, freq * clk_div); in exynos_dwmci_get_clk()
187 return sclk / clk_div; in exynos_dwmci_get_clk()
A Djz_mmc.c325 u8 clk_div = 0; in jz_mmc_set_ios() local
328 while ((real_rate > mmc->clock) && (clk_div < 7)) { in jz_mmc_set_ios()
330 clk_div++; in jz_mmc_set_ios()
332 writel(clk_div & MSC_CLKRT_CLK_RATE_MASK, priv->regs + MSC_CLKRT); in jz_mmc_set_ios()
A Dmeson_gx_mmc.c47 unsigned int clk, clk_src, clk_div; in meson_mmc_config_clock() local
62 clk_div = DIV_ROUND_UP(clk, mmc->clock); in meson_mmc_config_clock()
80 meson_mmc_clk |= clk_div; in meson_mmc_config_clock()
/drivers/spi/
A Drk_spi.c95 uint clk_div = DIV_ROUND_UP(priv->input_rate, speed); in rkspi_set_clk() local
104 if (clk_div > 0xfffe) { in rkspi_set_clk()
105 clk_div = 0xfffe; in rkspi_set_clk()
107 __func__, speed, priv->input_rate / clk_div); in rkspi_set_clk()
111 clk_div = (clk_div + 1) & 0xfffe; in rkspi_set_clk()
113 debug("spi speed %u, div %u\n", speed, clk_div); in rkspi_set_clk()
115 clrsetbits_le32(&priv->regs->baudr, 0xffff, clk_div); in rkspi_set_clk()
A Dti_qspi.c114 uint clk_div; in ti_qspi_set_speed() local
117 clk_div = 0; in ti_qspi_set_speed()
119 clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1; in ti_qspi_set_speed()
122 if (clk_div > QSPI_CLK_DIV_MAX) in ti_qspi_set_speed()
123 clk_div = QSPI_CLK_DIV_MAX; in ti_qspi_set_speed()
125 debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div); in ti_qspi_set_speed()
131 writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl); in ti_qspi_set_speed()
A Ddesignware_spi.c694 u16 clk_div; in dw_spi_set_speed() local
703 clk_div = priv->bus_clk_rate / speed; in dw_spi_set_speed()
704 clk_div = (clk_div + 1) & 0xfffe; in dw_spi_set_speed()
705 dw_write(priv, DW_SPI_BAUDR, clk_div); in dw_spi_set_speed()
711 dev_dbg(bus, "speed=%d clk_div=%d\n", priv->freq, clk_div); in dw_spi_set_speed()
/drivers/video/sunxi/
A Dsunxi_lcd.c47 int clk_div, clk_double, ret; in sunxi_lcd_enable() local
57 &clk_div, &clk_double, false); in sunxi_lcd_enable()
58 lcdc_tcon0_mode_set(lcdc, edid, clk_div, false, in sunxi_lcd_enable()
A Dsunxi_display.c636 int clk_div, clk_double, pin; local
655 lcdc_pll_set(ccm, 0, mode->pixclock_khz, &clk_div, &clk_double,
659 lcdc_tcon0_mode_set(lcdc, &timing, clk_div, for_ext_vga_dac,
665 int *clk_div, int *clk_double, argument
684 lcdc_pll_set(ccm, 1, mode->pixclock_khz, clk_div, clk_double,
739 int clk_div, int clk_double, argument
764 SUNXI_HDMI_PLL_CTRL_DIV(clk_div));
952 int __maybe_unused clk_div, clk_double; local
965 sunxi_lcdc_tcon1_mode_set(mode, &clk_div, &clk_double, 0, monitor);
966 sunxi_hdmi_mode_set(mode, clk_div, clk_double, monitor);
[all …]
A Dlcdc.c73 int clk_div, bool for_ext_vga_dac, in lcdc_tcon0_mode_set() argument
89 SUNXI_LCDC_TCON0_DCLK_DIV(clk_div), &lcdc->tcon0_dclk); in lcdc_tcon0_mode_set()
213 int *clk_div, int *clk_double, bool is_composite) in lcdc_pll_set() argument
333 *clk_div = best_m; in lcdc_pll_set()
/drivers/video/tegra/
A Ddc-pwm-backlight.c38 u32 clk_div; member
62 (priv->clk_div << PM_CLK_DIVIDER_SHIFT) | in tegra_pwm_backlight_set_brightness()
120 priv->clk_div = in tegra_pwm_backlight_probe()
/drivers/led/
A Dled_bcm6358.c120 unsigned int clk_div; in bcm6358_led_probe() local
129 clk_div = dev_read_u32_default(dev, "brcm,clk-div", in bcm6358_led_probe()
131 switch (clk_div) { in bcm6358_led_probe()
/drivers/serial/
A Dserial_msm_geni.c167 static int get_clk_div_rate(u32 baud, u64 sampling_rate, u32 *clk_div) in get_clk_div_rate() argument
180 *clk_div = ser_clk / desired_clk; in get_clk_div_rate()
233 static inline void geni_serial_baud(phys_addr_t base_address, u32 clk_div, in geni_serial_baud() argument
239 s_clk_cfg |= (clk_div << CLK_DIV_SHFT); in geni_serial_baud()
249 u32 clk_div; in msm_serial_setbrg() local
254 clk_rate = get_clk_div_rate(baud, priv->oversampling, &clk_div); in msm_serial_setbrg()
264 geni_serial_baud(priv->base, clk_div, baud); in msm_serial_setbrg()
/drivers/i2c/
A Dmxc_i2c.c119 u8 clk_div; in i2c_imx_get_clk() local
139 clk_div = 0; in i2c_imx_get_clk()
141 clk_div = ARRAY_SIZE(i2c_clk_div) - 1; in i2c_imx_get_clk()
143 for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++) in i2c_imx_get_clk()
147 return clk_div; in i2c_imx_get_clk()
A Ds3c24x0_i2c.h61 unsigned clk_div; member
A Dexynos_hs_i2c.c178 i2c_bus->clk_div = i; in hsi2c_get_clk_details()
199 n_clkdiv = i2c_bus->clk_div; in hsi2c_ch_init()
A Dgeni_i2c.c70 u8 clk_div; member
134 val = (itr->clk_div << CLK_DIV_SHFT) | SER_CLK_EN; in qcom_geni_i2c_conf()
A Dtegra_i2c.c120 int clk_div_stdfst_mode = readl(&i2c_bus->regs->clk_div) >> 16; in i2c_init_controller()
/drivers/usb/host/
A Ddwc3-octeon-glue.c70 static u8 clk_div[OCTEON_H_CLKDIV_SEL] = {1, 2, 4, 6, 8, 16, 24, 32}; variable
224 for (div = ARRAY_SIZE(clk_div) - 1; div >= 0; div--) { in dwc3_octeon_clocks_start()
225 h_clk_rate = gd->bus_clk / clk_div[div]; in dwc3_octeon_clocks_start()
/drivers/clk/rockchip/
A Dclk_rk3399.c505 #define I2C_CLK_REG_VALUE(bus, clk_div) \ argument
506 ((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT | \
515 #define I2C_PMUCLK_REG_VALUE(bus, clk_div) \ argument
516 ((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT)

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