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Searched refs:clk_id (Results 1 – 25 of 30) sorted by relevance

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/drivers/clk/
A Dclk_versal.c102 u32 clk_id; member
291 ret = versal_pm_clock_get_topology(clock[clk_id].clk_id, j, in versal_clock_get_topology()
339 ret = versal_pm_clock_get_parents(clock[clk_id].clk_id, j, in versal_clock_get_parents()
376 if (clk_id == PM_CLK_REF_CLK || clk_id == PM_CLK_MUXED_IRO || clk_id == PM_CLK_EMIO) in versal_clock_get_ref_rate()
713 u32 clk_id; in versal_clk_get_rate() local
718 clk_id = priv->clk[id].clk_id; in versal_clk_get_rate()
729 u32 clk_id; in versal_clk_set_rate() local
736 clk_id = priv->clk[id].clk_id; in versal_clk_set_rate()
754 clk_id = versal_clock_get_parentid(clk_id); in versal_clk_set_rate()
766 u32 clk_id; in versal_clk_enable() local
[all …]
/drivers/clk/exynos/
A Dclk.c22 unsigned long clk_id; in samsung_clk_register_mux() local
28 clk_id = SAMSUNG_TO_CLK_ID(cmu_id, m->id); in samsung_clk_register_mux()
29 clk_dm(clk_id, clk); in samsung_clk_register_mux()
42 unsigned long clk_id; in samsung_clk_register_div() local
48 clk_id = SAMSUNG_TO_CLK_ID(cmu_id, d->id); in samsung_clk_register_div()
49 clk_dm(clk_id, clk); in samsung_clk_register_div()
62 unsigned long clk_id; in samsung_clk_register_gate() local
68 clk_id = SAMSUNG_TO_CLK_ID(cmu_id, g->id); in samsung_clk_register_gate()
69 clk_dm(clk_id, clk); in samsung_clk_register_gate()
A Dclk-pll.c148 unsigned long clk_id; in samsung_clk_register_pll() local
152 clk_id = SAMSUNG_TO_CLK_ID(cmu_id, pll_clk->id); in samsung_clk_register_pll()
153 clk_dm(clk_id, clk); in samsung_clk_register_pll()
/drivers/clk/rockchip/
A Dclk_rk3588.c137 switch (clk_id) { in rk3588_center_get_clk()
203 switch (clk_id) { in rk3588_center_set_clk()
269 switch (clk_id) { in rk3588_top_get_clk()
315 switch (clk_id) { in rk3588_top_set_clk()
367 switch (clk_id) { in rk3588_i2c_get_clk()
426 switch (clk_id) { in rk3588_i2c_set_clk()
477 switch (clk_id) { in rk3588_spi_get_clk()
522 switch (clk_id) { in rk3588_spi_set_clk()
560 switch (clk_id) { in rk3588_pwm_get_clk()
606 switch (clk_id) { in rk3588_pwm_set_clk()
[all …]
A Dclk_rk3568.c230 switch (clk_id) { in rk3568_i2c_get_pmuclk()
251 switch (clk_id) { in rk3568_i2c_set_pmuclk()
269 switch (clk_id) { in rk3568_pwm_get_pmuclk()
292 switch (clk_id) { in rk3568_pwm_set_pmuclk()
602 switch (clk_id) { in rk3568_cpll_div_get_rate()
657 switch (clk_id) { in rk3568_cpll_div_set_rate()
717 switch (clk_id) { in rk3568_bus_get_clk()
756 switch (clk_id) { in rk3568_bus_set_clk()
798 switch (clk_id) { in rk3568_perimid_get_clk()
836 switch (clk_id) { in rk3568_perimid_set_clk()
[all …]
A Dclk_rk3576.c130 switch (clk_id) { in rk3576_bus_get_clk()
179 switch (clk_id) { in rk3576_bus_set_clk()
236 switch (clk_id) { in rk3576_top_get_clk()
296 switch (clk_id) { in rk3576_top_set_clk()
366 switch (clk_id) { in rk3576_i2c_get_clk()
438 switch (clk_id) { in rk3576_i2c_set_clk()
490 switch (clk_id) { in rk3576_spi_get_clk()
544 switch (clk_id) { in rk3576_spi_set_clk()
582 switch (clk_id) { in rk3576_pwm_get_clk()
624 switch (clk_id) { in rk3576_pwm_set_clk()
[all …]
A Dclk_px30.c292 switch (clk_id) { in px30_i2c_get_clk()
325 switch (clk_id) { in px30_i2c_set_clk()
425 switch (clk_id) { in px30_i2s_get_clk()
456 switch (clk_id) { in px30_i2s_set_clk()
515 switch (clk_id) { in px30_mmc_get_clk()
546 switch (clk_id) { in px30_mmc_set_clk()
613 switch (clk_id) { in px30_pwm_get_clk()
638 switch (clk_id) { in px30_pwm_set_clk()
718 switch (clk_id) { in px30_spi_get_clk()
743 switch (clk_id) { in px30_spi_set_clk()
[all …]
A Dclk_rk3528.c209 ulong clk_id) in rk3528_ppll_matrix_get_rate() argument
215 switch (clk_id) { in rk3528_ppll_matrix_get_rate()
257 switch (clk_id) { in rk3528_ppll_matrix_set_rate()
305 switch (clk_id) { in rk3528_cgpll_matrix_get_rate()
413 switch (clk_id) { in rk3528_cgpll_matrix_set_rate()
527 switch (clk_id) { in rk3528_i2c_get_clk()
614 switch (clk_id) { in rk3528_i2c_set_clk()
682 switch (clk_id) { in rk3528_spi_get_clk()
727 switch (clk_id) { in rk3528_spi_set_clk()
754 switch (clk_id) { in rk3528_pwm_get_clk()
[all …]
A Dclk_rk3128.c40 static int rkclk_set_pll(struct rk3128_cru *cru, enum rk_clk_id clk_id, in rkclk_set_pll() argument
43 int pll_id = rk_pll_id(clk_id); in rkclk_set_pll()
241 enum rk_clk_id clk_id) in rkclk_pll_get_rate() argument
245 int pll_id = rk_pll_id(clk_id); in rkclk_pll_get_rate()
259 shift = clk_shift[clk_id]; in rkclk_pll_get_rate()
260 mask = clk_mask[clk_id]; in rkclk_pll_get_rate()
352 switch (clk_id) { in rk3128_peri_get_pclk()
376 switch (clk_id) { in rk3128_peri_set_pclk()
426 switch (clk_id) { in rk3128_vop_set_clk()
457 static ulong rk3128_vop_get_rate(struct rk3128_cru *cru, ulong clk_id) in rk3128_vop_get_rate() argument
[all …]
A Dclk_rk3328.c221 switch (clk_id) { in rkclk_set_pll()
341 switch (clk_id) { in rk3328_i2c_get_clk()
373 switch (clk_id) { in rk3328_i2c_set_clk()
452 switch (clk_id) { in rk3328_mmc_get_clk()
475 ulong clk_id, ulong set_rate) in rk3328_mmc_set_clk() argument
480 switch (clk_id) { in rk3328_mmc_set_clk()
510 return rk3328_mmc_get_clk(cru, clk_id); in rk3328_mmc_set_clk()
591 switch (clk_id) { in rk3328_vop_get_clk()
616 ulong clk_id, uint hz) in rk3328_vop_set_clk() argument
625 switch (clk_id) { in rk3328_vop_set_clk()
[all …]
A Dclk_rk3368.c166 switch (clk_id) { in rk3368_mmc_get_clk()
257 ulong clk_id = clk->id; in rk3368_mmc_set_clk() local
263 switch (clk_id) { in rk3368_mmc_set_clk()
281 return rk3368_mmc_get_clk(cru, clk_id); in rk3368_mmc_set_clk()
387 switch (clk_id) { in rk3368_spi_get_clk()
389 spiclk = &spi_clkregs[clk_id - SCLK_SPI0]; in rk3368_spi_get_clk()
393 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id); in rk3368_spi_get_clk()
412 switch (clk_id) { in rk3368_spi_set_clk()
414 spiclk = &spi_clkregs[clk_id - SCLK_SPI0]; in rk3368_spi_set_clk()
418 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id); in rk3368_spi_set_clk()
[all …]
A Dclk_rk3308.c651 switch (clk_id) { in rk3308_bus_get_clk()
685 switch (clk_id) { in rk3308_bus_set_clk()
707 return rk3308_bus_get_clk(priv, clk_id); in rk3308_bus_set_clk()
715 switch (clk_id) { in rk3308_peri_get_clk()
748 switch (clk_id) { in rk3308_peri_set_clk()
770 return rk3308_peri_get_clk(priv, clk_id); in rk3308_peri_set_clk()
778 switch (clk_id) { in rk3308_audio_get_clk()
807 switch (clk_id) { in rk3308_audio_set_clk()
825 return rk3308_peri_get_clk(priv, clk_id); in rk3308_audio_set_clk()
833 switch (clk_id) { in rk3308_crypto_get_clk()
[all …]
A Dclk_rv1126.c189 ulong clk_id) in rv1126_i2c_get_pmuclk() argument
194 switch (clk_id) { in rv1126_i2c_get_pmuclk()
219 switch (clk_id) { in rv1126_i2c_set_pmuclk()
241 switch (clk_id) { in rv1126_pwm_get_pmuclk()
269 switch (clk_id) { in rv1126_pwm_set_pmuclk()
595 switch (clk_id) { in rv1126_pdbus_get_clk()
643 switch (clk_id) { in rv1126_pdbus_set_clk()
689 switch (clk_id) { in rv1126_pdphp_get_clk()
716 switch (clk_id) { in rv1126_pdphp_set_clk()
766 switch (clk_id) { in rv1126_i2c_get_clk()
[all …]
A Dclk_rk3399.c522 switch (clk_id) { in rk3399_i2c_get_clk()
563 switch (clk_id) { in rk3399_i2c_set_clk()
593 return rk3399_i2c_get_clk(cru, clk_id); in rk3399_i2c_set_clk()
637 switch (clk_id) { in rk3399_spi_get_clk()
662 switch (clk_id) { in rk3399_spi_set_clk()
688 switch (clk_id) { in rk3399_vop_set_clk()
729 switch (clk_id) { in rk3399_mmc_get_clk()
782 ulong clk_id, ulong set_rate) in rk3399_mmc_set_clk() argument
784 switch (clk_id) { in rk3399_mmc_set_clk()
1545 switch (clk_id) { in rk3399_i2c_get_pmuclk()
[all …]
A Dclk_rv1108.c48 static inline int rv1108_pll_id(enum rk_clk_id clk_id) in rv1108_pll_id() argument
52 switch (clk_id) { in rv1108_pll_id()
55 id = clk_id - 1; in rv1108_pll_id()
61 printf("invalid pll id:%d\n", clk_id); in rv1108_pll_id()
69 static int rkclk_set_pll(struct rv1108_cru *cru, enum rk_clk_id clk_id, in rkclk_set_pll() argument
72 int pll_id = rv1108_pll_id(clk_id); in rkclk_set_pll()
122 enum rk_clk_id clk_id) in rkclk_pll_get_rate() argument
126 int pll_id = rv1108_pll_id(clk_id); in rkclk_pll_get_rate()
421 switch (clk_id) { in rv1108_i2c_get_clk()
458 switch (clk_id) { in rv1108_i2c_set_clk()
[all …]
A Dclk_rk3036.c47 static int rkclk_set_pll(struct rk3036_cru *cru, enum rk_clk_id clk_id, in rkclk_set_pll() argument
50 int pll_id = rk_pll_id(clk_id); in rkclk_set_pll()
173 enum rk_clk_id clk_id) in rkclk_pll_get_rate() argument
177 int pll_id = rk_pll_id(clk_id); in rkclk_pll_get_rate()
191 shift = clk_shift[clk_id]; in rkclk_pll_get_rate()
192 mask = clk_mask[clk_id]; in rkclk_pll_get_rate()
A Dclk_rk322x.c45 static int rkclk_set_pll(struct rk322x_cru *cru, enum rk_clk_id clk_id, in rkclk_set_pll() argument
48 int pll_id = rk_pll_id(clk_id); in rkclk_set_pll()
175 enum rk_clk_id clk_id) in rkclk_pll_get_rate() argument
179 int pll_id = rk_pll_id(clk_id); in rkclk_pll_get_rate()
193 shift = clk_shift[clk_id]; in rkclk_pll_get_rate()
194 mask = clk_mask[clk_id]; in rkclk_pll_get_rate()
A Dclk_rk3188.c88 static int rkclk_set_pll(struct rk3188_cru *cru, enum rk_clk_id clk_id, in rkclk_set_pll() argument
91 int pll_id = rk_pll_id(clk_id); in rkclk_set_pll()
229 enum rk_clk_id clk_id) in rkclk_pll_get_rate() argument
233 int pll_id = rk_pll_id(clk_id); in rkclk_pll_get_rate()
242 shift = clk_shift[clk_id]; in rkclk_pll_get_rate()
A Dclk_rk3066.c83 static int rk3066_clk_set_pll(struct rk3066_cru *cru, enum rk_clk_id clk_id, in rk3066_clk_set_pll() argument
86 int pll_id = rk_pll_id(clk_id); in rk3066_clk_set_pll()
220 enum rk_clk_id clk_id) in rk3066_clk_pll_get_rate() argument
224 int pll_id = rk_pll_id(clk_id); in rk3066_clk_pll_get_rate()
233 shift = clk_shift[clk_id]; in rk3066_clk_pll_get_rate()
/drivers/clk/ti/
A Dclk-k3.c28 u32 clk_id; member
45 u32 dev_id, u32 clk_id) in clk_add_map() argument
50 clk, data, dev_id, clk_id); in clk_add_map()
57 map->clk_id = clk_id; in clk_add_map()
193 pdata->soc_dev_clk_data[j].clk_id); in ti_clk_probe()
202 static int _clk_cmp(u32 dev_id, u32 clk_id, const struct clk_map *map) in _clk_cmp() argument
204 if (map->dev_id == dev_id && map->clk_id == clk_id) in _clk_cmp()
207 (map->dev_id == dev_id && map->clk_id > clk_id)) in _clk_cmp()
218 result = _clk_cmp(dev_id, clk_id, &map[idx]); in bsearch()
274 data->map[clk->id].clk_id, rate); in ti_clk_set_rate()
[all …]
/drivers/spi/
A Dmxs_spi.c51 int clk_id; /* ID of the SSP clock */ member
58 unsigned int clk_id; member
325 priv->clk_id = p1a->arg[0]; in mxs_spi_probe()
330 (unsigned int)priv->regs, priv->max_freq, priv->clk_id); in mxs_spi_probe()
336 priv->clk_id = plat->clk_id; in mxs_spi_probe()
397 int clkid = priv->clk_id - MXS_SSP_IMX28_CLKID_SSP0; in mxs_spi_set_speed()
399 int clkid = priv->clk_id - MXS_SSP_IMX23_CLKID_SSP0; in mxs_spi_set_speed()
466 plat->clk_id = prop[1]; in mxs_of_to_plat()
470 plat->dma_id, plat->clk_id); in mxs_of_to_plat()
/drivers/misc/
A Dk3_avs.c62 int clk_id; member
238 int k3_avs_notify_freq(int dev_id, int clk_id, u32 freq) in k3_avs_notify_freq() argument
249 if (vd->dev_id != dev_id || vd->clk_id != clk_id) in k3_avs_notify_freq()
425 vd->clk_id = phandle_args.args[1]; in k3_avs_probe()
428 vd->dev_id, vd->clk_id); in k3_avs_probe()
471 .clk_id = 0, /* main sysclk0 */
483 .clk_id = 0, /* ARM clock */
504 .clk_id = 0, /* ARM clock */
534 .clk_id = 2, /* ARM clock */
/drivers/firmware/
A Dti_sci.h361 u8 clk_id; member
382 u8 clk_id; member
420 u8 clk_id; member
437 u8 clk_id; member
468 u8 clk_id; member
511 u8 clk_id; member
567 u8 clk_id; member
585 u8 clk_id; member
A Dti_sci.c1033 u32 dev_id, u8 clk_id, in ti_sci_set_clock_state() argument
1057 req.clk_id = clk_id; in ti_sci_set_clock_state()
1107 req.clk_id = clk_id; in ti_sci_cmd_get_clock_state()
1163 u32 dev_id, u8 clk_id) in ti_sci_cmd_idle_clock() argument
1182 u32 dev_id, u8 clk_id) in ti_sci_cmd_put_clock() argument
1317 req.clk_id = clk_id; in ti_sci_cmd_clk_set_parent()
1362 req.clk_id = clk_id; in ti_sci_cmd_clk_get_parent()
1409 req.clk_id = clk_id; in ti_sci_cmd_clk_get_num_parents()
1468 req.clk_id = clk_id; in ti_sci_cmd_clk_get_match_freq()
1527 req.clk_id = clk_id; in ti_sci_cmd_clk_set_freq()
[all …]
/drivers/usb/host/
A Dehci-mxs.c137 u32 phandle, phy_reg, clk_reg, clk_id; in ehci_usb_ofdata_to_platdata() local
178 ret = ofnode_read_u32_index(phy_node, "clocks", 1, &clk_id); in ehci_usb_ofdata_to_platdata()
193 if (clk_id == CLK_USB_PHY0) in ehci_usb_ofdata_to_platdata()
196 if (clk_id == CLK_USB_PHY1) in ehci_usb_ofdata_to_platdata()
199 debug("%s: pll_reg: 0x%p clk_id: %d\n", __func__, port->pll, clk_id); in ehci_usb_ofdata_to_platdata()

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