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Searched refs:clk_sel (Results 1 – 6 of 6) sorted by relevance

/drivers/clk/sophgo/
A Dclk-ip.c417 int clk_sel = 1; in mmux_get_rate() local
424 clk_sel = 0; in mmux_get_rate()
431 val = mmux->div_init[clk_sel]; in mmux_get_rate()
439 int clk_sel = 1; in mmux_set_rate() local
447 clk_sel = 0; in mmux_set_rate()
453 if (mmux->div_init[clk_sel] > 0) in mmux_set_rate()
465 u8 clk_sel, index; in mmux_set_parent() local
480 clk_sel = mmux->parent_infos[i].clk_sel; in mmux_set_parent()
483 if (clk_sel) in mmux_set_parent()
484 cv1800b_clk_clrbit(mmux->base, &mmux->clk_sel); in mmux_set_parent()
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A Dclk-ip.h16 u8 clk_sel; member
85 struct cv1800b_clk_regbit clk_sel; member
245 .clk_sel = CV1800B_CLK_REGBIT(_clk_sel_offset, \
A Dclk-cv1800b.c598 int clk_sel, parent, idx; in cv1800b_register_clk() local
601 clk_sel = cv1800b_clk_getbit(base, &mmux->clk_sel) ? 0 : 1; in cv1800b_register_clk()
602 parent = cv1800b_clk_getfield(base, &mmux->mux[clk_sel]); in cv1800b_register_clk()
604 if (clk_sel == mmux->parent_infos[idx].clk_sel && in cv1800b_register_clk()
/drivers/clk/imx/
A Dclk-imx93.c21 enum clk_sel { enum
56 enum clk_sel sel;
/drivers/clk/rockchip/
A Dclk_px30.c1597 u32 clk_sel; in px30_pmu_uart0_get_clk() local
1621 clk_sel = bitfield_extract_by_mask(con, UART0_CLK_SEL_MASK); in px30_pmu_uart0_get_clk()
1623 switch (clk_sel) { in px30_pmu_uart0_get_clk()
1655 u32 clk_sel; in px30_pmu_uart0_set_clk() local
1660 clk_sel = UART0_CLK_SEL_UART0; in px30_pmu_uart0_set_clk()
1664 clk_sel = UART0_CLK_SEL_UART0; in px30_pmu_uart0_set_clk()
1668 clk_sel = UART0_CLK_SEL_UART0_FRAC; in px30_pmu_uart0_set_clk()
1679 clk_sel << UART0_CLK_SEL_SHIFT); in px30_pmu_uart0_set_clk()
A Dclk_rv1126.c641 int src_clk_div, clk_sel; in rv1126_pdbus_set_clk() local
647 clk_sel = ACLK_PDBUS_SEL_GPLL; in rv1126_pdbus_set_clk()
650 clk_sel = ACLK_PDBUS_SEL_CPLL; in rv1126_pdbus_set_clk()
655 clk_sel << ACLK_PDBUS_SEL_SHIFT | in rv1126_pdbus_set_clk()

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