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Searched refs:clk_src (Results 1 – 13 of 13) sorted by relevance

/drivers/spi/
A Dmxc_spi.c186 u32 clk_src; in spi_cfg_mxc() local
191 clk_src = mxc_get_clock(MXC_CSPI_CLK); in spi_cfg_mxc()
193 div = DIV_ROUND_UP(clk_src, max_hz); in spi_cfg_mxc()
197 max_hz, div, clk_src / (4 << div)); in spi_cfg_mxc()
221 u32 clk_src = clk_get_rate(&mxcs->clk); in spi_cfg_mxc() local
223 u32 clk_src = mxc_get_clock(MXC_CSPI_CLK); in spi_cfg_mxc()
242 if (clk_src > max_hz) { in spi_cfg_mxc()
243 pre_div = (clk_src - 1) / max_hz; in spi_cfg_mxc()
/drivers/i2c/
A Dmtk_i2c.c342 static int mtk_i2c_calculate_speed(uint clk_src, in mtk_i2c_calculate_speed() argument
366 opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed); in mtk_i2c_calculate_speed()
394 if ((clk_src / (2 * sample_cnt * step_cnt)) > target_speed) { in mtk_i2c_calculate_speed()
428 uint clk_src; in mtk_i2c_set_speed() local
435 clk_src = clk_get_rate(&priv->clk_main) / I2C_DEFAULT_CLK_DIV; in mtk_i2c_set_speed()
439 ret = mtk_i2c_calculate_speed(clk_src, MAX_FS_MODE_SPEED, in mtk_i2c_set_speed()
447 ret = mtk_i2c_calculate_speed(clk_src, priv->speed, in mtk_i2c_set_speed()
461 ret = mtk_i2c_calculate_speed(clk_src, priv->speed, in mtk_i2c_set_speed()
/drivers/mmc/
A Dmeson_gx_mmc.c47 unsigned int clk, clk_src, clk_div; in meson_mmc_config_clock() local
57 clk_src = CLK_SRC_DIV2; in meson_mmc_config_clock()
60 clk_src = CLK_SRC_24M; in meson_mmc_config_clock()
79 meson_mmc_clk |= clk_src; in meson_mmc_config_clock()
/drivers/phy/marvell/
A Dcomphy_cp110.c36 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
38 ((clk_src) << 17) | COMPHY_FW_FORMAT(mode, 0, speeds))
604 cfg->comphy_map_data[lane].clk_src = in comphy_cp110_init_serdes_map()
664 ptr_comphy_map->clk_src, in comphy_cp110_init()
A Dcomphy_core.h28 bool clk_src; member
/drivers/video/nexell/soc/
A Ds5pxx18_soc_disptop_clk.h37 u32 clk_src);
A Ds5pxx18_soc_disptop_clk.c152 u32 clk_src) in nx_disp_top_clkgen_set_clock_source() argument
164 read_value |= clk_src << clksrcsel_pos; in nx_disp_top_clkgen_set_clock_source()
A Ds5pxx18_soc_dpc.h200 void nx_dpc_set_clock_source(u32 module_index, u32 index, u32 clk_src);
A Ds5pxx18_soc_dpc.c252 void nx_dpc_set_clock_source(u32 module_index, u32 index, u32 clk_src) in nx_dpc_set_clock_source() argument
262 read_value |= clk_src << clksrcsel_pos; in nx_dpc_set_clock_source()
/drivers/clk/rockchip/
A Dclk_rk3588.c1337 u32 reg, clk_src, uart_src, div; in rk3588_uart_set_rate() local
1341 clk_src = CLK_UART_SRC_SEL_GPLL; in rk3588_uart_set_rate()
1345 clk_src = CLK_UART_SRC_SEL_CPLL; in rk3588_uart_set_rate()
1349 clk_src = CLK_UART_SRC_SEL_GPLL; in rk3588_uart_set_rate()
1353 clk_src = CLK_UART_SRC_SEL_GPLL; in rk3588_uart_set_rate()
1396 (clk_src << CLK_UART_SRC_SEL_SHIFT) | in rk3588_uart_set_rate()
1446 u32 clk_src, div; in rk3588_pciephy_set_rate() local
1449 clk_src = CLK_PCIE_PHY_REF_SEL_24M; in rk3588_pciephy_set_rate()
1452 clk_src = CLK_PCIE_PHY_REF_SEL_PPLL; in rk3588_pciephy_set_rate()
1459 (clk_src << CLK_PCIE_PHY0_REF_SEL_SHIFT)); in rk3588_pciephy_set_rate()
[all …]
A Dclk_rk3576.c1662 u32 reg, clk_src, p_rate; in rk3576_uart_frac_set_rate() local
1666 clk_src = CLK_UART_SRC_SEL_CPLL; in rk3576_uart_frac_set_rate()
1669 clk_src = CLK_UART_SRC_SEL_OSC; in rk3576_uart_frac_set_rate()
1672 clk_src = CLK_UART_SRC_SEL_GPLL; in rk3576_uart_frac_set_rate()
1794 u32 reg, clk_src = 0, div = 0; in rk3576_uart_set_rate() local
1797 clk_src = CLK_UART_SEL_GPLL; in rk3576_uart_set_rate()
1800 clk_src = CLK_UART_SEL_CPLL; in rk3576_uart_set_rate()
1803 clk_src = CLK_UART_SEL_FRAC0; in rk3576_uart_set_rate()
1806 clk_src = CLK_UART_SEL_FRAC1; in rk3576_uart_set_rate()
1809 clk_src = CLK_UART_SEL_FRAC2; in rk3576_uart_set_rate()
[all …]
A Dclk_px30.c421 u32 clk_src = priv->gpll_hz / 2; in px30_i2s_get_clk() local
442 return clk_src * n / m; in px30_i2s_get_clk()
447 u32 clk_src; in px30_i2s_set_clk() local
451 clk_src = priv->gpll_hz / 2; in px30_i2s_set_clk()
452 rational_best_approximation(hz, clk_src, in px30_i2s_set_clk()
A Dclk_rk3568.c2249 u32 reg, clk_src, uart_src, div; in rk3568_uart_set_rate() local
2253 clk_src = CLK_UART_SRC_SEL_GPLL; in rk3568_uart_set_rate()
2257 clk_src = CLK_UART_SRC_SEL_CPLL; in rk3568_uart_set_rate()
2261 clk_src = CLK_UART_SRC_SEL_GPLL; in rk3568_uart_set_rate()
2265 clk_src = CLK_UART_SRC_SEL_GPLL; in rk3568_uart_set_rate()
2308 (clk_src << CLK_UART_SRC_SEL_SHIFT) | in rk3568_uart_set_rate()

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