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Searched refs:con (Results 1 – 25 of 25) sorted by relevance

/drivers/clk/rockchip/
A Dclk_rk3588.c135 u32 con, sel, rate; in rk3588_center_get_clk() local
364 u32 sel, con; in rk3588_i2c_get_clk() local
473 u32 sel, con; in rk3588_spi_get_clk() local
558 u32 sel, con; in rk3588_pwm_get_clk() local
637 u32 div, sel, con, prate; in rk3588_adc_get_clk() local
728 u32 sel, con, div, prate; in rk3588_mmc_get_clk() local
882 u32 div, con, parent; in rk3588_aux16m_get_clk() local
931 u32 div, sel, con, parent; in rk3588_aclk_vop_get_clk() local
1045 u32 div, sel, con, parent; in rk3588_dclk_vop_get_clk() local
1207 u32 con, div; in rk3588_gmac_get_clk() local
[all …]
A Dclk_rk3576.c128 u32 con, sel, div, rate; in rk3576_bus_get_clk() local
363 u32 sel, con; in rk3576_i2c_get_clk() local
488 u32 sel, con; in rk3576_spi_get_clk() local
580 u32 sel, con; in rk3576_pwm_get_clk() local
650 u32 div, sel, con, prate; in rk3576_adc_get_clk() local
1087 u32 div, sel, con, parent; in rk3576_dclk_vop_get_clk() local
1243 u32 div, sel, con, parent; in rk3576_clk_csihost_get_clk() local
1281 con = 151; in rk3576_clk_csihost_set_clk()
1343 u32 div, sel, con, parent; in rk3576_dclk_ebc_get_clk() local
1519 u32 con, div, src, p_rate; in rk3576_gmac_get_clk() local
[all …]
A Dclk_rv1126.c192 u32 div, con; in rv1126_i2c_get_pmuclk() local
239 u32 div, sel, con; in rv1126_pwm_get_pmuclk() local
316 u32 div, con; in rv1126_spi_get_pmuclk() local
344 u32 div, con; in rv1126_pdpmu_get_pmuclk() local
568 u32 con, div; in rv1126_pdcore_get_clk() local
687 u32 con, div, parent; in rv1126_pdphp_get_clk() local
739 u32 con, div; in rv1126_pdaudio_get_clk() local
764 u32 div, con; in rv1126_i2c_get_clk() local
826 u32 div, con; in rv1126_spi_get_clk() local
853 u32 div, sel, con; in rv1126_pwm_get_clk() local
[all …]
A Dclk_rk3568.c604 con = 78; in rk3568_cpll_div_get_rate()
609 con = 79; in rk3568_cpll_div_get_rate()
614 con = 79; in rk3568_cpll_div_get_rate()
619 con = 80; in rk3568_cpll_div_get_rate()
624 con = 82; in rk3568_cpll_div_get_rate()
629 con = 80; in rk3568_cpll_div_get_rate()
634 con = 81; in rk3568_cpll_div_get_rate()
639 con = 81; in rk3568_cpll_div_get_rate()
659 con = 78; in rk3568_cpll_div_set_rate()
664 con = 79; in rk3568_cpll_div_set_rate()
[all …]
A Dclk_px30.c265 con = readl(mode); in rkclk_pll_get_rate()
290 u32 div, con; in px30_i2c_get_clk() local
481 u32 div, con; in px30_nandc_get_clk() local
585 u32 div, con; in px30_sfc_get_clk() local
611 u32 div, con; in px30_pwm_get_clk() local
664 u32 div, con; in px30_saradc_get_clk() local
690 u32 div, con; in px30_tsadc_get_clk() local
716 u32 div, con; in px30_spi_get_clk() local
1053 u32 con; in px30_i2s1_mclk_get_clk() local
1534 u32 div, con; in px30_pclk_pmu_get_pmuclk() local
[all …]
A Dclk_rk3308.c181 u32 div, con, con_id; in rk3308_i2c_get_clk() local
291 u32 div, con, con_id; in rk3308_mmc_get_clk() local
363 u32 div, con; in rk3308_saradc_get_clk() local
365 con = readl(&cru->clksel_con[34]); in rk3308_saradc_get_clk()
391 u32 div, con; in rk3308_tsadc_get_clk() local
419 u32 div, con, con_id; in rk3308_spi_get_clk() local
478 u32 div, con; in rk3308_pwm_get_clk() local
561 con = readl(&cru->clksel_con[8]); in rk3308_vop_get_clk()
564 div = con & DCLK_VOP_DIV_MASK; in rk3308_vop_get_clk()
831 u32 div, con, parent; in rk3308_crypto_get_clk() local
[all …]
A Dclk_rk3128.c244 u32 con; in rkclk_pll_get_rate() local
258 con = readl(&cru->cru_mode_con); in rkclk_pll_get_rate()
267 con = readl(&pll->con0); in rkclk_pll_get_rate()
270 con = readl(&pll->con1); in rkclk_pll_get_rate()
285 u32 con; in rockchip_mmc_get_clk() local
350 u32 div, con; in rk3128_peri_get_pclk() local
359 div = con >> 12 & 0x3; in rk3128_peri_get_pclk()
459 u32 div, con, parent; in rk3128_vop_get_rate() local
464 div = con & 0x1f; in rk3128_vop_get_rate()
469 div = (con >> 8) & 0x1f; in rk3128_vop_get_rate()
[all …]
A Dclk_rk3528.c307 con = 0; in rk3528_cgpll_matrix_get_rate()
314 con = 0; in rk3528_cgpll_matrix_get_rate()
321 con = 1; in rk3528_cgpll_matrix_get_rate()
327 con = 1; in rk3528_cgpll_matrix_get_rate()
333 con = 1; in rk3528_cgpll_matrix_get_rate()
341 con = 2; in rk3528_cgpll_matrix_get_rate()
347 con = 2; in rk3528_cgpll_matrix_get_rate()
354 con = 2; in rk3528_cgpll_matrix_get_rate()
360 con = 3; in rk3528_cgpll_matrix_get_rate()
368 con = 4; in rk3528_cgpll_matrix_get_rate()
[all …]
A Dclk_rk3328.c339 u32 div, con; in rk3328_i2c_get_clk() local
343 con = readl(&cru->clksel_con[34]); in rk3328_i2c_get_clk()
450 u32 div, con, con_id; in rk3328_mmc_get_clk() local
515 u32 div, con; in rk3328_pwm_get_clk() local
517 con = readl(&cru->clksel_con[24]); in rk3328_pwm_get_clk()
589 u32 div, con, parent; in rk3328_vop_get_clk() local
620 u32 con, parent; in rk3328_vop_set_clk() local
640 con = (con & DCLK_LCDC_SEL_MASK) >> DCLK_LCDC_SEL_SHIFT; in rk3328_vop_set_clk()
641 if (con) { in rk3328_vop_set_clk()
667 u32 div, con; in rk3328_hdmiphy_get_clk() local
[all …]
A Dclk_rk3036.c176 uint32_t con; in rkclk_pll_get_rate() local
190 con = readl(&cru->cru_mode_con); in rkclk_pll_get_rate()
194 switch ((con & mask) >> shift) { in rkclk_pll_get_rate()
200 con = readl(&pll->con0); in rkclk_pll_get_rate()
203 con = readl(&pll->con1); in rkclk_pll_get_rate()
218 u32 con; in rockchip_mmc_get_clk() local
223 con = readl(&cru->cru_clksel_con[12]); in rockchip_mmc_get_clk()
224 mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT; in rockchip_mmc_get_clk()
225 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; in rockchip_mmc_get_clk()
229 con = readl(&cru->cru_clksel_con[12]); in rockchip_mmc_get_clk()
[all …]
A Dclk_rk3066.c223 u32 con; in rk3066_clk_pll_get_rate() local
232 con = readl(&cru->cru_mode_con); in rk3066_clk_pll_get_rate()
239 con = readl(&pll->con0); in rk3066_clk_pll_get_rate()
242 con = readl(&pll->con1); in rk3066_clk_pll_get_rate()
256 u32 con; in rk3066_clk_mmc_get_clk() local
261 con = readl(&cru->cru_clksel_con[12]); in rk3066_clk_mmc_get_clk()
266 con = readl(&cru->cru_clksel_con[11]); in rk3066_clk_mmc_get_clk()
271 con = readl(&cru->cru_clksel_con[12]); in rk3066_clk_mmc_get_clk()
321 u32 con; in rk3066_clk_spi_get_clk() local
325 con = readl(&cru->cru_clksel_con[25]); in rk3066_clk_spi_get_clk()
[all …]
A Dclk_rk3288.c546 uint32_t con; in rkclk_pll_get_rate() local
555 con = readl(&cru->cru_mode_con); in rkclk_pll_get_rate()
562 con = readl(&pll->con0); in rkclk_pll_get_rate()
565 con = readl(&pll->con1); in rkclk_pll_get_rate()
580 u32 con; in rockchip_mmc_get_clk() local
585 con = readl(&cru->cru_clksel_con[12]); in rockchip_mmc_get_clk()
591 con = readl(&cru->cru_clksel_con[11]); in rockchip_mmc_get_clk()
597 con = readl(&cru->cru_clksel_con[12]); in rockchip_mmc_get_clk()
663 u32 con; in rockchip_spi_get_clk() local
667 con = readl(&cru->cru_clksel_con[25]); in rockchip_spi_get_clk()
[all …]
A Dclk_rk322x.c178 uint32_t con; in rkclk_pll_get_rate() local
192 con = readl(&cru->cru_mode_con); in rkclk_pll_get_rate()
196 switch ((con & mask) >> shift) { in rkclk_pll_get_rate()
202 con = readl(&pll->con0); in rkclk_pll_get_rate()
205 con = readl(&pll->con1); in rkclk_pll_get_rate()
219 u32 con; in rockchip_mmc_get_clk() local
225 con = readl(&cru->cru_clksel_con[11]); in rockchip_mmc_get_clk()
226 mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT; in rockchip_mmc_get_clk()
227 con = readl(&cru->cru_clksel_con[12]); in rockchip_mmc_get_clk()
232 con = readl(&cru->cru_clksel_con[11]); in rockchip_mmc_get_clk()
[all …]
A Dclk_rk3188.c232 uint32_t con; in rkclk_pll_get_rate() local
241 con = readl(&cru->cru_mode_con); in rkclk_pll_get_rate()
248 con = readl(&pll->con0); in rkclk_pll_get_rate()
251 con = readl(&pll->con1); in rkclk_pll_get_rate()
265 u32 con; in rockchip_mmc_get_clk() local
270 con = readl(&cru->cru_clksel_con[12]); in rockchip_mmc_get_clk()
275 con = readl(&cru->cru_clksel_con[11]); in rockchip_mmc_get_clk()
280 con = readl(&cru->cru_clksel_con[12]); in rockchip_mmc_get_clk()
330 u32 con; in rockchip_spi_get_clk() local
334 con = readl(&cru->cru_clksel_con[25]); in rockchip_spi_get_clk()
[all …]
A Dclk_pll.c368 u32 con = 0, shift, mask; in rk3036_pll_get_rate() local
372 con = readl(base + pll->mode_offset); in rk3036_pll_get_rate()
377 mode = (con & mask) >> shift; in rk3036_pll_get_rate()
386 con = readl(base + pll->con_offset); in rk3036_pll_get_rate()
560 u32 con = 0, shift, mode; in rk3588_pll_get_rate() local
563 con = readl(base + pll->mode_offset); in rk3588_pll_get_rate()
574 con = readl(base + pll->con_offset); in rk3588_pll_get_rate()
575 m = (con & RK3588_PLLCON0_M_MASK) >> in rk3588_pll_get_rate()
578 p = (con & RK3588_PLLCON1_P_MASK) >> in rk3588_pll_get_rate()
580 s = (con & RK3588_PLLCON1_S_MASK) >> in rk3588_pll_get_rate()
[all …]
A Dclk_rk3399.c520 u32 div, con; in rk3399_i2c_get_clk() local
525 div = I2C_CLK_DIV_VALUE(con, 1); in rk3399_i2c_get_clk()
529 div = I2C_CLK_DIV_VALUE(con, 2); in rk3399_i2c_get_clk()
533 div = I2C_CLK_DIV_VALUE(con, 3); in rk3399_i2c_get_clk()
537 div = I2C_CLK_DIV_VALUE(con, 5); in rk3399_i2c_get_clk()
541 div = I2C_CLK_DIV_VALUE(con, 6); in rk3399_i2c_get_clk()
545 div = I2C_CLK_DIV_VALUE(con, 7); in rk3399_i2c_get_clk()
727 u32 div, con; in rk3399_mmc_get_clk() local
1543 u32 div, con; in rk3399_i2c_get_pmuclk() local
1548 div = I2C_CLK_DIV_VALUE(con, 0); in rk3399_i2c_get_pmuclk()
[all …]
A Dclk_rv1108.c149 uint32_t con = readl(&cru->clksel_con[24]); in rv1108_mac_set_clk() local
153 if ((con >> MAC_PLL_SEL_SHIFT) & MAC_PLL_SEL_GPLL) in rv1108_mac_set_clk()
174 u32 con = readl(&cru->clksel_con[27]); in rv1108_sfc_set_clk() local
419 u32 div, con; in rv1108_i2c_get_clk() local
423 con = readl(&cru->clksel_con[19]); in rv1108_i2c_get_clk()
428 con = readl(&cru->clksel_con[19]); in rv1108_i2c_get_clk()
433 con = readl(&cru->clksel_con[20]); in rv1108_i2c_get_clk()
438 con = readl(&cru->clksel_con[20]); in rv1108_i2c_get_clk()
493 u32 div, con; in rv1108_mmc_get_clk() local
496 con = readl(&cru->clksel_con[26]); in rv1108_mmc_get_clk()
[all …]
A Dclk_rk3368.c69 uint32_t con; in rkclk_pll_get_rate() local
72 con = readl(&pll->con3); in rkclk_pll_get_rate()
78 con = readl(&pll->con0); in rkclk_pll_get_rate()
79 no = ((con & PLL_OD_MASK) >> PLL_OD_SHIFT) + 1; in rkclk_pll_get_rate()
80 nr = ((con & PLL_NR_MASK) >> PLL_NR_SHIFT) + 1; in rkclk_pll_get_rate()
81 con = readl(&pll->con1); in rkclk_pll_get_rate()
82 nf = ((con & PLL_NF_MASK) >> PLL_NF_SHIFT) + 1; in rkclk_pll_get_rate()
163 u32 div, con, con_id, rate; in rk3368_mmc_get_clk() local
180 con = readl(&cru->clksel_con[con_id]); in rk3368_mmc_get_clk()
181 switch (con & MMC_PLL_SEL_MASK) { in rk3368_mmc_get_clk()
[all …]
/drivers/sound/
A Dsamsung-i2s.c63 unsigned int con = readl(&i2s_reg->con); in i2s_txctrl() local
67 con |= CON_ACTIVE; in i2s_txctrl()
68 con &= ~CON_TXCH_PAUSE; in i2s_txctrl()
70 con |= CON_TXCH_PAUSE; in i2s_txctrl()
71 con &= ~CON_ACTIVE; in i2s_txctrl()
75 writel(con, &i2s_reg->con); in i2s_txctrl()
282 if (!(CON_TXFIFO_FULL & (readl(&i2s_reg->con)))) { in i2s_transfer_tx_data()
335 writel(CON_RESET, &i2s_reg->con); in i2s_tx_init()
/drivers/i2c/
A Drk_i2c.c87 debug("i2c_con: 0x%08x\n", readl(&regs->con)); in rk_i2c_show_regs()
111 writel(I2C_CON_EN | I2C_CON_START, &regs->con); in rk_i2c_send_start_bit()
139 writel(I2C_CON_EN | I2C_CON_STOP, &regs->con); in rk_i2c_send_stop_bit()
161 writel(0, &i2c->regs->con); in rk_i2c_disable()
173 uint con = 0; in rk_i2c_read() local
198 con = I2C_CON_EN; in rk_i2c_read()
205 con = I2C_CON_EN | I2C_CON_LASTACK; in rk_i2c_read()
214 con |= I2C_CON_MOD(I2C_MODE_RX); in rk_i2c_read()
216 con |= I2C_CON_MOD(I2C_MODE_TRX); in rk_i2c_read()
218 writel(con, &regs->con); in rk_i2c_read()
[all …]
/drivers/sysinfo/
A Dgazerbeam.c64 int mc4, mc2, sc, mc2_sc, con; in _read_sysinfo_variant_data() local
116 con = dm_gpio_get_value(&priv->var_gpios[CON_GPIO_NO]); in _read_sysinfo_variant_data()
117 if (con < 0) { in _read_sysinfo_variant_data()
119 dev->name, con); in _read_sysinfo_variant_data()
120 return con; in _read_sysinfo_variant_data()
123 priv->variant = con ? VAR_CON : VAR_CPU; in _read_sysinfo_variant_data()
/drivers/mmc/
A Domap_hsmmc.c286 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con); in mmc_init_stream()
307 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con); in mmc_init_stream()
378 writel(readl(&mmc_base->con) | DDR, &mmc_base->con); in omap_hsmmc_set_timing()
380 writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con); in omap_hsmmc_set_timing()
444 u32 con; in omap_hsmmc_wait_dat0() local
450 con = readl(&mmc_base->con); in omap_hsmmc_wait_dat0()
451 writel(con | CON_CLKEXTFREE | CON_PADEN, &mmc_base->con); in omap_hsmmc_wait_dat0()
462 writel(con, &mmc_base->con); in omap_hsmmc_wait_dat0()
1399 &mmc_base->con);
1404 &mmc_base->con);
[all …]
/drivers/power/
A Dexynos-tmu.c269 unsigned te_code, con; in tmu_setup_parameters() local
320 con = readl(&reg->tmu_control); in tmu_setup_parameters()
321 con |= THERM_TRIP_EN | CORE_EN | (info->tmu_mux << 20); in tmu_setup_parameters()
323 writel(con, &reg->tmu_control); in tmu_setup_parameters()
/drivers/gpio/
A Ds5p_gpio.c78 value = readl(&bank->con); in s5p_gpio_cfg_pin()
81 writel(value, &bank->con); in s5p_gpio_cfg_pin()
109 value = readl(&bank->con); in s5p_gpio_get_cfg_pin()
/drivers/video/
A Dstb_truetype.h3910 con->width = pw; in stbrp_init_target()
3911 con->height = ph; in stbrp_init_target()
3912 con->x = 0; in stbrp_init_target()
3913 con->y = 0; in stbrp_init_target()
3914 con->bottom_y = 0; in stbrp_init_target()
3923 if (con->x + rects[i].w > con->width) { in stbrp_pack_rects()
3924 con->x = 0; in stbrp_pack_rects()
3925 con->y = con->bottom_y; in stbrp_pack_rects()
3927 if (con->y + rects[i].h > con->height) in stbrp_pack_rects()
3933 if (con->y + rects[i].h > con->bottom_y) in stbrp_pack_rects()
[all …]

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