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Searched refs:cs (Results 1 – 25 of 149) sorted by relevance

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/drivers/ddr/marvell/axp/
A Dddr3_write_leveling.c107 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_hw()
229 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_wl_supplement()
431 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_wl_supplement()
530 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_hw_reg_dimm()
619 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_hw_reg_dimm()
679 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_sw()
722 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_sw()
837 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_sw()
914 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_sw_reg_dimm()
955 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_sw_reg_dimm()
[all …]
A Dddr3_read_leveling.c91 u32 delay, phase, pup, cs; in ddr3_read_leveling_hw() local
97 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_read_leveling_hw()
121 cs, pup); in ddr3_read_leveling_hw()
128 (u32) cs, 1); in ddr3_read_leveling_hw()
202 for (cs = 0; cs < dram_info->num_cs; cs++) { in ddr3_read_leveling_sw()
619 * cs)); in ddr3_read_leveling_single_cs_rl_mode()
622 cs)); in ddr3_read_leveling_single_cs_rl_mode()
729 for (cs = 0; cs < dram_info->num_cs; cs++) { in ddr3_read_leveling_single_cs_rl_mode()
1024 * cs)); in ddr3_read_leveling_single_cs_window_mode()
1027 cs)); in ddr3_read_leveling_single_cs_window_mode()
[all …]
A Dddr3_spd.c907 for (cs = 0; cs < MAX_CS; cs++) {
931 for (cs = 0; cs < MAX_CS; cs++) {
947 for (cs = 0; cs < MAX_CS; cs++) {
1024 for (cs = 0; cs < MAX_CS; cs++) {
1047 for (cs = 0; cs < MAX_CS; cs++) {
1058 for (cs = 0; cs < MAX_CS; cs++) {
1073 for (cs = 0; cs < MAX_CS; cs++) {
1085 for (cs = 0; cs < MAX_CS; cs++) {
1122 for (cs = 0; cs < MAX_CS; cs++) {
1133 for (cs = 0; cs < MAX_CS; cs++) {
[all …]
A Dddr3_dfs.c117 u32 cs = 0; in ddr3_dfs_high_2_low() local
195 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_high_2_low()
441 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_high_2_low()
467 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_high_2_low()
498 u32 cs = 0; in ddr3_dfs_high_2_low()
675 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_high_2_low()
773 u32 cs = 0; in ddr3_dfs_low_2_high() local
1004 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_low_2_high()
1136 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_low_2_high()
1162 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_low_2_high()
[all …]
A Dddr3_dqs.c132 u32 cs, ecc, reg; in ddr3_dqs_centralization_rx() local
150 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dqs_centralization_rx()
153 (u32) cs, 1); in ddr3_dqs_centralization_rx()
214 u32 cs, ecc, reg; in ddr3_dqs_centralization_tx() local
232 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dqs_centralization_tx()
235 (u32) cs, 1); in ddr3_dqs_centralization_tx()
1088 cs, in ddr3_special_pattern_i_search()
1239 cs, in ddr3_special_pattern_ii_search()
1274 cs, 1); in ddr3_set_dqs_centralization_results()
1277 cs, 1); in ddr3_set_dqs_centralization_results()
[all …]
/drivers/memory/
A Dti-gpmc.c292 gpmc_show_regs(cs, desc); in gpmc_cs_show_timings()
413 cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000, in set_gpmc_timing_reg()
710 if (cs >= gpmc_cs_num) { in gpmc_cs_request()
730 gpmc_cs_disable_mem(cs); in gpmc_cs_request()
737 gpmc_cs_enable_mem(cs); in gpmc_cs_request()
745 if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) { in gpmc_cs_free()
750 gpmc_cs_disable_mem(cs); in gpmc_cs_free()
1010 u32 val, cs; in gpmc_probe_generic_child() local
1050 cs); in gpmc_probe_generic_child()
1109 gpmc_cs_enable_mem(cs); in gpmc_probe_generic_child()
[all …]
A Dstm32-fmc2-ebi.c231 int cs) in stm32_fmc2_ebi_check_mux() argument
243 int cs) in stm32_fmc2_ebi_check_waitcfg() argument
256 int cs) in stm32_fmc2_ebi_check_sync_trans() argument
268 int cs) in stm32_fmc2_ebi_mp25_check_cclk() argument
278 int cs) in stm32_fmc2_ebi_mp25_check_clk_period() argument
290 int cs) in stm32_fmc2_ebi_check_async_trans() argument
315 int cs) in stm32_fmc2_ebi_check_address_hold() argument
332 int cs) in stm32_fmc2_ebi_check_clk_period() argument
345 int cs) in stm32_fmc2_ebi_check_cclk() argument
347 if (cs) in stm32_fmc2_ebi_check_cclk()
[all …]
A Dti-aemif.c19 static void aemif_configure(int cs, struct aemif_config *cfg) in aemif_configure() argument
25 tmp |= (1 << cs); in aemif_configure()
30 tmp |= (1 << cs); in aemif_configure()
34 aemif_cs_configure(cs, cfg); in aemif_configure()
39 int cs; in aemif_init() local
46 for (cs = 0; cs < num_cs; cs++) in aemif_init()
47 aemif_configure(cs, config + cs); in aemif_init()
/drivers/spi/
A Dspi-aspeed-smc.c268 for (cs = priv->num_cs; cs < plat->max_cs; cs++) in ast2500_adjust_decoded_size()
277 for (cs = priv->num_cs - 1; cs >= 0; cs--) { in ast2500_adjust_decoded_size()
402 for (cs = priv->num_cs; cs < plat->max_cs; cs++) in ast2600_adjust_decoded_size()
411 for (cs = priv->num_cs - 1; cs >= 0; cs--) { in ast2600_adjust_decoded_size()
774 for (cs = 1; cs < plat->max_cs; cs++) { in aspeed_spi_decoded_base_calculate()
789 for (cs = 0; cs < plat->max_cs; cs++) { in aspeed_spi_decoded_range_set()
829 for (cs = 0; cs < plat->max_cs; cs++) in aspeed_spi_decoded_ranges_sanity()
840 for (cs = 0; cs < plat->max_cs; cs++) { in aspeed_spi_decoded_ranges_sanity()
853 for (cs = plat->max_cs - 1; cs > 0; cs--) { in aspeed_spi_decoded_ranges_sanity()
947 for (cs = 0; cs < priv->num_cs; cs++) { in aspeed_spi_ctrl_init()
[all …]
A Dmt7620_spi.c103 writel(cfg, &ms->m[cs]->cfg); in mt7620_spi_master_setup()
105 writel(SPI_HIGH, &ms->m[cs]->ctl); in mt7620_spi_master_setup()
111 mt7620_spi_master_setup(ms, cs); in mt7620_spi_set_cs()
159 ret = mt7620_spi_busy_poll(ms, cs); in mt7620_spi_read()
177 writel(*buf++, &ms->m[cs]->data); in mt7620_spi_write()
180 ret = mt7620_spi_busy_poll(ms, cs); in mt7620_spi_write()
196 int cs, ret = 0; in mt7620_spi_xfer() local
207 cs = spi_chip_select(dev); in mt7620_spi_xfer()
208 if (cs < 0 || cs >= MT7620_SPI_NUM_CS) { in mt7620_spi_xfer()
214 mt7620_spi_set_cs(ms, cs, true); in mt7620_spi_xfer()
[all …]
A Domap3_spi.c36 unsigned int cs; member
47 writel(val, &priv->regs->channel[priv->cs].chconf); in omap3_spi_write_chconf()
49 readl(&priv->regs->channel[priv->cs].chconf); in omap3_spi_write_chconf()
56 readl(&priv->regs->channel[priv->cs].chctrl); in omap3_spi_set_enable()
83 readl(&priv->regs->channel[priv->cs].chstat)); in omap3_spi_write()
131 writel(0, &priv->regs->channel[priv->cs].tx); in omap3_spi_read()
140 readl(&priv->regs->channel[priv->cs].chstat)); in omap3_spi_read()
369 for (priv->cs = 0 ; priv->cs < OMAP4_MCSPI_CHAN_NB ; priv->cs++) in spi_reset()
371 priv->cs = 0; in spi_reset()
396 priv->cs = slave_plat->cs[0]; in omap3_spi_claim_bus()
[all …]
A Dfsl_espi.c29 unsigned int cs; member
88 com |= ESPI_COM_CS(cs); in fsl_spi_cs_activate()
311 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) & in espi_claim_bus()
317 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) in espi_claim_bus()
322 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) in espi_claim_bus()
325 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) in espi_claim_bus()
329 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) in espi_claim_bus()
333 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) in espi_claim_bus()
386 if (!spi_cs_is_valid(bus, cs)) in spi_setup_slave()
462 espi_claim_bus(fsl, fsl->cs); in fsl_espi_claim_bus()
[all …]
A Dspi-uclass.c227 return plat ? plat->cs[0] : -ENOENT; in spi_chip_select()
245 ret = ops->cs_info(bus, cs, &info); in spi_find_chip_select()
265 if (plat->cs[0] == cs) { in spi_find_chip_select()
286 return spi_cs_info(bus, cs, &info); in spi_cs_is_valid()
314 ret = spi_find_chip_select(bus, cs, &dev); in spi_find_bus_and_cs()
316 dev_dbg(bus, "%s: No cs %d\n", __func__, cs); in spi_find_bus_and_cs()
342 ret = spi_find_chip_select(bus, cs, &dev); in spi_get_bus_and_cs()
401 ret = spi_find_chip_select(bus, cs, &dev); in _spi_get_bus_and_cs()
410 __func__, dev_name, busnum, cs, drv_name); in _spi_get_bus_and_cs()
418 plat->cs[0] = cs; in _spi_get_bus_and_cs()
[all …]
A Dmxc_spi.c141 u32 cs = slave_plat->cs[0]; in mxc_spi_cs_activate() local
159 u32 cs = slave_plat->cs[0]; in mxc_spi_cs_deactivate() local
199 ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) | in spi_cfg_mxc()
261 MXC_CSPICTRL_SELCHAN(cs); in spi_cfg_mxc()
285 (ss_pol << (cs + MXC_CSPICON_SSPOL)); in spi_cfg_mxc()
287 (sclkpol << (cs + MXC_CSPICON_POL)); in spi_cfg_mxc()
289 (sclkctl << (cs + MXC_CSPICON_CTL)); in spi_cfg_mxc()
291 (sclkpha << (cs + MXC_CSPICON_PHA)); in spi_cfg_mxc()
473 ret = spi_cfg_mxc(mxcs, cs); in mxc_spi_claim_bus_internal()
502 unsigned int bus, unsigned int cs) in setup_cs_gpio() argument
[all …]
A Dbcmbca_hsspi.c118 if (cs >= priv->num_cs) { in bcmbca_hsspi_cs_info()
119 dev_err(bus, "no cs %u\n", cs); in bcmbca_hsspi_cs_info()
182 if (priv->cs_pols & BIT(plat->cs[0])) in bcmbca_hsspi_setup_clock()
183 set |= BIT(plat->cs[0]); in bcmbca_hsspi_setup_clock()
185 clr |= BIT(plat->cs[0]); in bcmbca_hsspi_setup_clock()
279 val |= (plat->cs[0] << SPI_CMD_PFL_SHIFT) & in bcmbca_hsspi_xfer()
329 if (plat->cs[0] >= priv->num_cs) { in bcmbca_hsspi_child_pre_probe()
330 dev_err(dev, "no cs %u\n", plat->cs[0]); in bcmbca_hsspi_child_pre_probe()
336 priv->cs_pols |= BIT(plat->cs[0]); in bcmbca_hsspi_child_pre_probe()
338 priv->cs_pols &= ~BIT(plat->cs[0]); in bcmbca_hsspi_child_pre_probe()
[all …]
/drivers/ddr/marvell/a38x/
A Dmv_ddr_regs.h118 #define CS_STRUCT_OFFS(cs) (CS_STRUCT_BASE + (cs) * 4) argument
121 #define CS_SIZE_OFFS(cs) (CS_SIZE_BASE + (cs) * 4) argument
124 #define CS_SIZE_HIGH_OFFS(cs) (CS_SIZE_HIGH_BASE + (cs)) argument
135 #define SDRAM_OP_CMD_CS_OFFS(cs) (SDRAM_OP_CMD_CS_BASE + (cs)) argument
231 #define RD_SMPL_DLY_CS_OFFS(cs) (RD_SMPL_DLY_CS_BASE + (cs) * 8) argument
236 #define RD_RDY_DLY_CS_OFFS(cs) (RD_RDY_DLY_CS_BASE + (cs) * 8) argument
268 #define CS_EXIST_OFFS(cs) (CS_EXIST_BASE + (cs)) argument
448 #define WL_PHY_REG(cs) (WL_PHY_BASE + (cs) * 0x4) argument
460 #define CTX_PHY_REG(cs) (CTX_PHY_BASE + (cs) * 0x4) argument
463 #define RL_PHY_REG(cs) (RL_PHY_BASE + (cs) * 0x4) argument
[all …]
/drivers/ddr/marvell/a38x/old/
A Dddr3_init.c197 u32 reg, cs; in ddr3_restore_and_set_final_windows() local
199 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_restore_and_set_final_windows()
201 reg |= (cs << 2); in ddr3_restore_and_set_final_windows()
244 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_save_and_set_training_windows()
246 switch (cs) { in ddr3_save_and_set_training_windows()
521 u32 cs; in ddr3_get_cs_num_from_reg() local
523 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_get_cs_num_from_reg()
524 if (cs_ena & (1 << cs)) in ddr3_get_cs_num_from_reg()
581 u32 reg, cs; in ddr3_fast_path_dynamic_cs_size_config() local
593 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_fast_path_dynamic_cs_size_config()
[all …]
/drivers/crypto/aspeed/
A Dcptra_sha.c48 struct cptra_sha *cs; in cptra_sha_init() local
75 cs = dev_get_priv(dev); in cptra_sha_init()
85 writel(0x0, cs->regs + CPTRA_SHA_DLEN); in cptra_sha_init()
88 reg = readl(cs->regs + CPTRA_SHA_MODE); in cptra_sha_init()
91 writel(reg, cs->regs + CPTRA_SHA_MODE); in cptra_sha_init()
105 struct cptra_sha *cs; in cptra_sha_update() local
111 cs = dev_get_priv(dev); in cptra_sha_update()
139 struct cptra_sha *cs; in cptra_sha_finish() local
143 cs = dev_get_priv(dev); in cptra_sha_finish()
147 writel(0x1, cs->regs + CPTRA_SHA_EXEC); in cptra_sha_finish()
[all …]
/drivers/mfd/
A Datmel-smc.c252 regmap_write(regmap, ATMEL_SMC_SETUP(cs), conf->setup); in atmel_smc_cs_conf_apply()
253 regmap_write(regmap, ATMEL_SMC_PULSE(cs), conf->pulse); in atmel_smc_cs_conf_apply()
254 regmap_write(regmap, ATMEL_SMC_CYCLE(cs), conf->cycle); in atmel_smc_cs_conf_apply()
255 regmap_write(regmap, ATMEL_SMC_MODE(cs), conf->mode); in atmel_smc_cs_conf_apply()
271 int cs, const struct atmel_smc_cs_conf *conf) in atmel_hsmc_cs_conf_apply() argument
290 void atmel_smc_cs_conf_get(struct regmap *regmap, int cs, in atmel_smc_cs_conf_get() argument
293 regmap_read(regmap, ATMEL_SMC_SETUP(cs), &conf->setup); in atmel_smc_cs_conf_get()
294 regmap_read(regmap, ATMEL_SMC_PULSE(cs), &conf->pulse); in atmel_smc_cs_conf_get()
295 regmap_read(regmap, ATMEL_SMC_CYCLE(cs), &conf->cycle); in atmel_smc_cs_conf_get()
296 regmap_read(regmap, ATMEL_SMC_MODE(cs), &conf->mode); in atmel_smc_cs_conf_get()
[all …]
/drivers/video/
A Dhitachi_tx18d42vm_lcd.c20 static void lcd_panel_spi_write(int cs, int clk, int mosi, in lcd_panel_spi_write() argument
25 gpio_direction_output(cs, 0); in lcd_panel_spi_write()
34 gpio_direction_output(cs, 1); in lcd_panel_spi_write()
50 int i, cs, clk, mosi, ret = 0; in hitachi_tx18d42vm_init() local
52 cs = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_CS); in hitachi_tx18d42vm_init()
56 if (cs == -1 || clk == -1 || mosi == 1) { in hitachi_tx18d42vm_init()
61 if (gpio_request(cs, "tx18d42vm-spi-cs") != 0 || in hitachi_tx18d42vm_init()
70 lcd_panel_spi_write(cs, clk, mosi, init_data[i], 16); in hitachi_tx18d42vm_init()
74 lcd_panel_spi_write(cs, clk, mosi, 0x00ad, 16); /* display on */ in hitachi_tx18d42vm_init()
79 gpio_free(cs); in hitachi_tx18d42vm_init()
/drivers/ddr/fsl/
A Dmpc85xx_ddr_gen3.c86 cs_sa = (regs->cs[i].bnds >> 16) & 0xfff; in fsl_ddr_set_memctl_regs()
87 cs_ea = regs->cs[i].bnds & 0xfff; in fsl_ddr_set_memctl_regs()
90 csn_bnds_backup = regs->cs[i].bnds; in fsl_ddr_set_memctl_regs()
98 csn, csn_bnds_backup, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
105 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
110 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
455 if (!(regs->cs[i].config & 0x80000000)) in fsl_ddr_set_memctl_regs()
458 ((regs->cs[i].config >> 14) & 0x3) + 2 + in fsl_ddr_set_memctl_regs()
459 ((regs->cs[i].config >> 8) & 0x7) + 12 + in fsl_ddr_set_memctl_regs()
460 ((regs->cs[i].config >> 0) & 0x7) + 8 + in fsl_ddr_set_memctl_regs()
[all …]
A Darm_ddr_gen3.c71 ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
72 ddr_out32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
76 ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
77 ddr_out32(&ddr->cs1_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
81 ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
86 ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
203 if (!(regs->cs[i].config & 0x80000000)) in fsl_ddr_set_memctl_regs()
206 ((regs->cs[i].config >> 14) & 0x3) + 2 + in fsl_ddr_set_memctl_regs()
207 ((regs->cs[i].config >> 8) & 0x7) + 12 + in fsl_ddr_set_memctl_regs()
208 ((regs->cs[i].config >> 0) & 0x7) + 8 + in fsl_ddr_set_memctl_regs()
[all …]
A Dmpc85xx_ddr_gen1.c30 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
31 out_be32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
34 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
35 out_be32(&ddr->cs1_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
38 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
39 out_be32(&ddr->cs2_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
42 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
43 out_be32(&ddr->cs3_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
A Dfsl_ddr_gen4.c127 (regs->cs[i].bnds & 0xfffefffe) >> 1); in fsl_ddr_set_memctl_regs()
129 (regs->cs[i].config & in fsl_ddr_set_memctl_regs()
132 ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
140 (regs->cs[i].bnds & 0xfffefffe) >> 1); in fsl_ddr_set_memctl_regs()
150 (regs->cs[i].bnds & 0xfffefffe) >> 1); in fsl_ddr_set_memctl_regs()
160 (regs->cs[i].bnds & 0xfffefffe) >> 1); in fsl_ddr_set_memctl_regs()
496 if (!(regs->cs[i].config & 0x80000000)) in fsl_ddr_set_memctl_regs()
499 ((regs->cs[i].config >> 14) & 0x3) + 2 + in fsl_ddr_set_memctl_regs()
500 ((regs->cs[i].config >> 8) & 0x7) + 12 + in fsl_ddr_set_memctl_regs()
501 ((regs->cs[i].config >> 4) & 0x3) + 0 + in fsl_ddr_set_memctl_regs()
[all …]
/drivers/watchdog/
A Dulp_wdog.c16 u32 cs; member
64 if (readl(&wdog->cs) & WDGCS_CMD32EN) { in ulp_watchdog_reset()
78 if (readl(&wdog->cs) & WDGCS_CMD32EN) { in ulp_watchdog_init()
89 while (!(readl(&wdog->cs) & WDGCS_ULK)) in ulp_watchdog_init()
98 WDGCS_FLG | WDOG_CS_PRES | WDGCS_INT), &wdog->cs); in ulp_watchdog_init()
101 WDGCS_FLG), &wdog->cs); in ulp_watchdog_init()
104 while (!(readl(&wdog->cs) & WDGCS_RCS)) in ulp_watchdog_init()
130 if (readl(&wdog->cs) & WDGCS_CMD32EN) { in reset_cpu()
141 while (!(readl(&wdog->cs) & WDGCS_ULK)) in reset_cpu()
150 WDGCS_INT), &wdog->cs); in reset_cpu()
[all …]

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