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Searched refs:cs_bitmask (Results 1 – 12 of 12) sorted by relevance

/drivers/ddr/marvell/a38x/old/
A Dddr_topology_def.h48 u8 cs_bitmask; member
A Dddr3_training.c268 u32 cs_bitmask; in calc_cs_num() local
275 cs_bitmask = tm->interface_params[if_id]. in calc_cs_num()
276 as_bus_params[bus_cnt].cs_bitmask; in calc_cs_num()
278 if ((cs_bitmask >> cs) & 1) in calc_cs_num()
474 as_bus_params[bus_cnt].cs_bitmask; in hws_ddr3_tip_init_controller()
731 as_bus_params[0].cs_bitmask != in ddr3_tip_rank_control()
744 as_bus_params[0].cs_bitmask; in ddr3_tip_rank_control()
1776 cs_bitmask = in ddr3_tip_write_cs_result()
1778 as_bus_params[bus_num].cs_bitmask; in ddr3_tip_write_cs_result()
1779 if (cs_bitmask != effective_cs) { in ddr3_tip_write_cs_result()
[all …]
A Dddr3_training_leveling.c51 cs_bitmask, c_cs); in hws_ddr3_tip_max_cs_get()
939 as_bus_params[bus_cnt].cs_bitmask; in ddr3_tip_calc_cs_mask()
941 as_bus_params[bus_cnt].cs_bitmask; in ddr3_tip_calc_cs_mask()
945 as_bus_params[bus_cnt].cs_bitmask; in ddr3_tip_calc_cs_mask()
A Dddr3_init.c231 cs_ena = tm->interface_params[0].as_bus_params[0].cs_bitmask; in ddr3_save_and_set_training_windows()
A Dddr3_training_static.c257 (bus_index % 4)].cs_bitmask].cs_num; in ddr3_tip_read_leveling_static_config()
A Dddr3_debug.c1157 as_bus_params[pup_id].cs_bitmask);
1472 as_bus_params[uj].cs_bitmask); in print_topology()
/drivers/ddr/marvell/a38x/
A Dddr3_training_leveling.c787 as_bus_params[bus_cnt].cs_bitmask; in ddr3_tip_calc_cs_mask()
789 as_bus_params[bus_cnt].cs_bitmask; in ddr3_tip_calc_cs_mask()
793 as_bus_params[bus_cnt].cs_bitmask; in ddr3_tip_calc_cs_mask()
1675 u8 cs_bitmask, u8 dis_auto_refresh) in mpr_rd_frmt_config() argument
1705 cs_bitmask_inv = ~cs_bitmask & SDRAM_OP_CMD_ALL_CS_MASK; in mpr_rd_frmt_config()
1747 u8 cs_bitmask = tm->interface_params[0].as_bus_params[0].cs_bitmask; in mv_ddr_rl_dqs_burst() local
1754 cs_bitmask, 1); in mv_ddr_rl_dqs_burst()
1823 reg_val = ((~(curr_cs_bitmask_inv & cs_bitmask) & SDRAM_OP_CMD_ALL_CS_MASK) << in mv_ddr_rl_dqs_burst()
2064 reg_val = (~cs_bitmask & SDRAM_OP_CMD_ALL_CS_MASK) << SDRAM_OP_CMD_CS_OFFS(0) | in mv_ddr_rl_dqs_burst()
2081 cs_bitmask, 0); in mv_ddr_rl_dqs_burst()
A Dmv_ddr_topology.c86 iface_params->as_bus_params[i].cs_bitmask = val; in mv_ddr_topology_map_update()
221 VALIDATE_ACTIVE(iface_params->as_bus_params[sphy].cs_bitmask, cs); in mv_ddr_cs_num_get()
A Dddr3_training.c509 as_bus_params[bus_cnt].cs_bitmask; in hws_ddr3_tip_init_controller()
716 cs_bitmask; in ddr3_tip_rev2_rank_control()
725 cs_bitmask & 0x1) != 0) { in ddr3_tip_rev2_rank_control()
732 cs_bitmask & 0x2) != 0) { in ddr3_tip_rev2_rank_control()
739 cs_bitmask & 0x4) != 0) { in ddr3_tip_rev2_rank_control()
746 cs_bitmask & 0x8) != 0) { in ddr3_tip_rev2_rank_control()
770 as_bus_params[0].cs_bitmask != in ddr3_tip_rev3_rank_control()
783 as_bus_params[0].cs_bitmask; in ddr3_tip_rev3_rank_control()
1896 cs_bitmask = in ddr3_tip_write_cs_result()
1898 as_bus_params[bus_num].cs_bitmask; in ddr3_tip_write_cs_result()
[all …]
A Dddr_topology_def.h24 u8 cs_bitmask; member
A Dmv_ddr_plat.c1279 cs_ena = tm->interface_params[0].as_bus_params[0].cs_bitmask; in ddr3_save_and_set_training_windows()
A Dddr3_debug.c1447 as_bus_params[uj].cs_bitmask); in print_topology()

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