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Searched refs:cs_ena (Results 1 – 15 of 15) sorted by relevance

/drivers/ddr/marvell/axp/
A Dddr3_spd.c664 cs_ena = 0;
676 cs_ena |= (0x1 << cs);
678 cs_ena |= (0x3 << cs);
680 cs_ena |= (0x7 << cs);
682 cs_ena |= (0xF << cs);
692 if (cs_ena > 0xF) {
948 if (cs_ena & (1 << cs))
983 reg = odt_config[cs_ena];
991 reg = cs_ena;
1048 if (cs_ena & (1 << cs))
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A Dddr3_write_leveling.c108 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_hw()
230 if (dram_info->cs_ena & (1 << cs)) { in ddr3_wl_supplement()
432 if (dram_info->cs_ena & (1 << cs)) { in ddr3_wl_supplement()
531 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_hw_reg_dimm()
620 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_hw_reg_dimm()
680 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_sw()
723 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_sw()
838 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_sw()
915 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_sw_reg_dimm()
956 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_sw_reg_dimm()
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A Dddr3_hw_training.c95 dram_info.cs_ena = ddr3_get_cs_ena_from_reg(); in ddr3_hw_training()
229 if (dram_info.cs_ena > 1) { in ddr3_hw_training()
320 if (dram_info.cs_ena > 1) { in ddr3_hw_training()
456 dram_info.cs_ena = 1; in ddr3_hw_training()
666 reg = (dram_info->cs_ena << REG_DRAM_TRAINING_CS_OFFS) | in ddr3_load_patterns()
714 tmp_cs = dram_info->cs_ena; in ddr3_save_training()
892 dram_info->cs_ena = 0x1; in ddr3_check_if_resume_mode()
901 dram_info->cs_ena = ddr3_get_cs_ena_from_reg(); in ddr3_check_if_resume_mode()
957 dram_info->cs_ena = 1; in ddr3_training_suspend_resume()
1090 u32 cs_ena, reg; in ddr3_odt_read_dynamic_config() local
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A Dddr3_init.c143 u32 cs_ena = ddr3_get_cs_ena_from_reg(); in ddr3_restore_and_set_final_windows() local
170 if (cs_ena & (1 << cs)) { in ddr3_restore_and_set_final_windows()
186 if (cs_ena & (1 << cs)) { in ddr3_restore_and_set_final_windows()
199 u32 cs_ena = ddr3_get_cs_ena_from_reg(); in ddr3_save_and_set_training_windows() local
233 if (cs_ena & (1 << cs)) { in ddr3_save_and_set_training_windows()
1051 u32 cs_ena = ddr3_get_cs_ena_from_reg(); in ddr3_get_cs_num_from_reg() local
1056 if (cs_ena & (1 << cs)) in ddr3_get_cs_num_from_reg()
A Dddr3_dfs.c196 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dfs_high_2_low()
442 if (dram_info->cs_ena & (1 << cs)) in ddr3_dfs_high_2_low()
468 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dfs_high_2_low()
676 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dfs_high_2_low()
1005 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dfs_low_2_high()
1009 reg |= odt_static[dram_info->cs_ena][cs]; in ddr3_dfs_low_2_high()
1137 if (dram_info->cs_ena & (1 << cs)) in ddr3_dfs_low_2_high()
1163 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dfs_low_2_high()
1436 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dfs_low_2_high()
A Dddr3_dqs.c151 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dqs_centralization_rx()
233 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dqs_centralization_tx()
334 if (dram_info->cs_ena & (1 << cs_tmp)) in ddr3_find_adll_limits()
1335 if (dram_info->cs_ena & (1 << cs)) { in ddr3_load_dqs_patterns()
1338 if (dram_info->cs_ena & (1 << cs_tmp)) in ddr3_load_dqs_patterns()
A Dddr3_read_leveling.c74 reg |= (dram_info->cs_ena << REG_DRAM_TRAINING_CS_OFFS); in ddr3_read_leveling_hw()
98 if (dram_info->cs_ena & (1 << cs)) { in ddr3_read_leveling_hw()
196 reg = (dram_info->cs_ena << REG_DRAM_TRAINING_CS_OFFS) | in ddr3_read_leveling_sw()
A Dxor.c51 if (dram_info->cs_ena & (1 << ui)) { in mv_sys_xor_init()
A Dddr3_hw_training.h253 u32 cs_ena; member
A Dddr3_pbs.c1560 if (dram_info->cs_ena & (1 << cs)) { in ddr3_load_pbs_patterns()
1563 if (dram_info->cs_ena & (1 << cs_tmp)) in ddr3_load_pbs_patterns()
/drivers/ddr/marvell/a38x/old/
A Dddr3_init.c180 u32 cs_ena = sys_env_get_cs_ena_from_reg(); in ddr3_restore_and_set_final_windows() local
194 if (ddr3_fast_path_dynamic_cs_size_config(cs_ena) != MV_OK) in ddr3_restore_and_set_final_windows()
200 if (cs_ena & (1 << cs)) { in ddr3_restore_and_set_final_windows()
212 u32 cs_ena; in ddr3_save_and_set_training_windows() local
231 cs_ena = tm->interface_params[0].as_bus_params[0].cs_bitmask; in ddr3_save_and_set_training_windows()
245 if (cs_ena & (1 << cs)) { in ddr3_save_and_set_training_windows()
519 u32 cs_ena = sys_env_get_cs_ena_from_reg(); in ddr3_get_cs_num_from_reg() local
524 if (cs_ena & (1 << cs)) in ddr3_get_cs_num_from_reg()
579 int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena) in ddr3_fast_path_dynamic_cs_size_config() argument
594 if (cs_ena & (1 << cs)) { in ddr3_fast_path_dynamic_cs_size_config()
A Dddr3_init.h362 int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena);
363 void ddr3_fast_path_static_cs_size_config(u32 cs_ena);
/drivers/ddr/marvell/a38x/
A Dxor.c21 void mv_sys_xor_init(u32 num_of_cs, u32 cs_ena, uint64_t cs_size, u32 base_delta) in mv_sys_xor_init() argument
38 if (cs_ena & (1 << ui)) { in mv_sys_xor_init()
52 if (cs_ena & (1 << ui)) { in mv_sys_xor_init()
342 u32 cs_ena = 0; in ddr3_new_tip_ecc_scrub() local
348 cs_ena |= 1 << cs_c; in ddr3_new_tip_ecc_scrub()
353 mv_sys_xor_init(max_cs, cs_ena, cs_mem_size, 0); in ddr3_new_tip_ecc_scrub()
A Dmv_ddr_plat.c1139 static int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena) in ddr3_fast_path_dynamic_cs_size_config() argument
1155 if (cs_ena & (1 << cs)) { in ddr3_fast_path_dynamic_cs_size_config()
1226 u32 cs_ena = mv_ddr_sys_env_get_cs_ena_from_reg(); in ddr3_restore_and_set_final_windows() local
1240 if (ddr3_fast_path_dynamic_cs_size_config(cs_ena) != MV_OK) in ddr3_restore_and_set_final_windows()
1246 if (cs_ena & (1 << cs)) { in ddr3_restore_and_set_final_windows()
1260 u32 cs_ena; in ddr3_save_and_set_training_windows() local
1279 cs_ena = tm->interface_params[0].as_bus_params[0].cs_bitmask; in ddr3_save_and_set_training_windows()
1293 if (cs_ena & (1 << cs)) { in ddr3_save_and_set_training_windows()
A Dddr3_init.h210 void ddr3_fast_path_static_cs_size_config(u32 cs_ena);

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