Home
last modified time | relevance | path

Searched refs:ctrl (Results 1 – 25 of 168) sorted by relevance

1234567

/drivers/mtd/nand/raw/brcmnand/
A Dbrcmnand.c824 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_set_cmd_addr() local
861 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_wr_corr_thresh() local
924 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_set_ecc_enabled() local
1437 if (ctrl->soc->ctlrdy_ack(ctrl->soc)) in brcmnand_irq()
2703 ctrl->soc->ctlrdy_ack(ctrl->soc); in brcmnand_resume()
2787 soc->ctrl = ctrl; in brcmnand_probe()
2848 ctrl->nand_fc = ctrl->nand_base + in brcmnand_probe()
2860 ctrl->nand_fc = ctrl->nand_base + in brcmnand_probe()
2957 ctrl->soc->ctlrdy_ack(ctrl->soc); in brcmnand_probe()
2983 host->ctrl = ctrl; in brcmnand_probe()
[all …]
/drivers/usb/host/
A Dxhci-mem.c114 xhci_dma_unmap(ctrl, ctrl->scratchpad->sp_array[0], in xhci_scratchpad_free()
116 xhci_dma_unmap(ctrl, ctrl->dcbaa->dev_context_ptrs[0], in xhci_scratchpad_free()
186 xhci_ring_free(ctrl, ctrl->event_ring); in xhci_cleanup()
187 xhci_ring_free(ctrl, ctrl->cmd_ring); in xhci_cleanup()
190 xhci_dma_unmap(ctrl, ctrl->erst.erst_dma_addr, in xhci_cleanup()
193 xhci_dma_unmap(ctrl, ctrl->dcbaa->dma, in xhci_cleanup()
403 buf = memalign(ctrl->page_size, num_sp * ctrl->page_size); in xhci_scratchpad_alloc()
542 ctrl->dcbaa->dma = xhci_dma_map(ctrl, ctrl->dcbaa, in xhci_mem_init()
548 ctrl->cmd_ring = xhci_ring_alloc(ctrl, 1, true); in xhci_mem_init()
569 ctrl->ir_set = &ctrl->run_regs->ir_set[0]; in xhci_mem_init()
[all …]
A Dxhci-ring.c59 if (ring == ctrl->event_ring) in last_trb()
80 if (ring == ctrl->event_ring) in last_trb_on_last_seg()
299 BUG_ON(prepare_ring(ctrl, ctrl->cmd_ring, EP_STATE_RUNNING)); in xhci_queue_command()
314 queue_trb(ctrl, ctrl->cmd_ring, false, fields); in xhci_queue_command()
355 if (ctrl->hci_version < 0x100 && !(ctrl->quirks & XHCI_MTK_HOST)) in xhci_td_remainder()
364 if ((ctrl->quirks & XHCI_MTK_HOST) && (ctrl->hci_version < 0x100)) in xhci_td_remainder()
421 inc_deq(ctrl, ctrl->event_ring); in xhci_acknowledge_event()
469 if (!event_ready(ctrl)) in xhci_wait_for_event()
525 xhci_acknowledge_event(ctrl); in reset_ep()
536 xhci_acknowledge_event(ctrl); in reset_ep()
[all …]
A Dehci-hcd.c194 ctrl->ops.set_usb_mode(ctrl); in ehci_reset()
746 status_reg = ctrl->ops.get_portsc_register(ctrl, port - 1); in ehci_submit_root()
841 switch (ctrl->ops.get_port_speed(ctrl, reg)) { in ehci_submit_root()
907 ctrl->ops.powerup_fixup(ctrl, status_reg, &reg); in ehci_submit_root()
1017 ctrl->ops = *ops; in ehci_setup_ops()
1173 rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor); in usb_lowlevel_init()
1176 if (!ctrl->hccr || !ctrl->hcor) in usb_lowlevel_init()
1186 rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor); in usb_lowlevel_init()
1713 ctrl->priv = ctrl; in ehci_register()
1724 ret = ctrl->ops.init_after_reset(ctrl); in ehci_register()
[all …]
A Dxhci.c757 if (ctrl->rootdev == 0) { in _xhci_alloc_device()
822 xhci_endpoint_copy(ctrl, ctrl->devs[slot_id]->in_ctx, in xhci_check_maxpacket()
1234 hccr = ctrl->hccr; in xhci_lowlevel_init()
1235 hcor = ctrl->hcor; in xhci_lowlevel_init()
1276 ctrl->hci_version = reg; in xhci_lowlevel_init()
1285 xhci_reset(ctrl->hcor); in xhci_lowlevel_stop()
1439 ctrl, hccr, hcor); in xhci_register()
1441 ctrl->dev = dev; in xhci_register()
1455 ctrl->hccr = hccr; in xhci_register()
1456 ctrl->hcor = hcor; in xhci_register()
[all …]
/drivers/ddr/microchip/
A Dddr2.c115 struct ddr2_ctrl_regs *ctrl; in ddr2_ctrl_init() local
117 ctrl = ioremap(PIC32_DDR2C_BASE, sizeof(*ctrl)); in ddr2_ctrl_init()
124 ddr_set_arbiter(ctrl, arb_params); in ddr2_ctrl_init()
140 &ctrl->refcfg); in ddr2_ctrl_init()
146 &ctrl->pwrcfg); in ddr2_ctrl_init()
190 &ctrl->dlycfg3); in ddr2_ctrl_init()
193 writel(0x0, &ctrl->odtcfg); in ddr2_ctrl_init()
194 writel(BIT(16), &ctrl->odtencfg); in ddr2_ctrl_init()
196 &ctrl->odtcfg); in ddr2_ctrl_init()
201 &ctrl->xfercfg); in ddr2_ctrl_init()
[all …]
/drivers/mtd/nand/raw/
A Dfsl_elbc_nand.c164 struct fsl_elbc_ctrl *ctrl = priv->ctrl; in set_addr() local
204 struct fsl_elbc_ctrl *ctrl = priv->ctrl; in fsl_elbc_run_command() local
255 struct fsl_elbc_ctrl *ctrl = priv->ctrl; in fsl_elbc_do_read() local
289 struct fsl_elbc_ctrl *ctrl = priv->ctrl; in fsl_elbc_cmdfunc() local
449 if (ctrl->oob || ctrl->column != 0 || in fsl_elbc_cmdfunc()
507 struct fsl_elbc_ctrl *ctrl = priv->ctrl; in fsl_elbc_write_buf() local
531 in_8(&ctrl->addr[ctrl->index] + len - 1); in fsl_elbc_write_buf()
544 struct fsl_elbc_ctrl *ctrl = priv->ctrl; in fsl_elbc_read_byte() local
547 if (ctrl->index < ctrl->read_bytes) in fsl_elbc_read_byte()
561 struct fsl_elbc_ctrl *ctrl = priv->ctrl; in fsl_elbc_read_buf() local
[all …]
A Dfsl_ifc_nand.c223 struct fsl_ifc_ctrl *ctrl = priv->ctrl; in set_addr() local
257 struct fsl_ifc_ctrl *ctrl = priv->ctrl; in fsl_ifc_run_command() local
332 struct fsl_ifc_ctrl *ctrl = priv->ctrl; in fsl_ifc_do_read() local
370 struct fsl_ifc_ctrl *ctrl = priv->ctrl; in fsl_ifc_cmdfunc() local
525 ctrl->index - ctrl->column); in fsl_ifc_cmdfunc()
576 struct fsl_ifc_ctrl *ctrl = priv->ctrl; in fsl_ifc_write_buf() local
604 struct fsl_ifc_ctrl *ctrl = priv->ctrl; in fsl_ifc_read_byte() local
611 if (ctrl->index < ctrl->read_bytes) { in fsl_ifc_read_byte()
628 struct fsl_ifc_ctrl *ctrl = priv->ctrl; in fsl_ifc_read_byte16() local
635 if (ctrl->index < ctrl->read_bytes) { in fsl_ifc_read_byte16()
[all …]
A Dkirkwood_nand.c19 u32 ctrl; /* 0x10470 */ member
33 unsigned int ctrl) in kw_nand_hwcontrol() argument
41 if (ctrl & NAND_CLE) in kw_nand_hwcontrol()
43 else if (ctrl & NAND_ALE) in kw_nand_hwcontrol()
71 data = readl(&nf_reg->ctrl); in kw_nand_select_chip()
73 writel(data, &nf_reg->ctrl); in kw_nand_select_chip()
/drivers/i2c/
A Di2c-microchip.c107 ctrl &= ~CTRL_SI; in mpfs_i2c_int_clear()
123 ctrl |= CTRL_ENS1; in mpfs_i2c_core_enable()
137 ctrl |= CTRL_STO; in mpfs_i2c_stop()
170 u8 clkval, ctrl; in mpfs_i2c_init() local
189 ctrl &= ~CLK_MASK; in mpfs_i2c_init()
195 ctrl |= clkval; in mpfs_i2c_init()
215 u8 ctrl; in mpfs_i2c_empty_rx() local
243 u8 ctrl; in mpfs_i2c_service_handler() local
340 u8 ctrl; in mpfs_i2c_check_service_change() local
373 u8 ctrl; in mpfs_i2c_xfer_msg() local
[all …]
/drivers/pinctrl/rockchip/
A Dpinctrl-rockchip-core.c24 struct rockchip_pin_ctrl *ctrl = priv->ctrl; in rockchip_verify_config() local
44 struct rockchip_pin_ctrl *ctrl = priv->ctrl; in rockchip_get_recalced_mux() local
68 struct rockchip_pin_ctrl *ctrl = priv->ctrl; in rockchip_get_mux_route() local
181 struct rockchip_pin_ctrl *ctrl = priv->ctrl; in rockchip_pinctrl_get_gpio_mux() local
225 struct rockchip_pin_ctrl *ctrl = priv->ctrl; in rockchip_set_mux() local
308 struct rockchip_pin_ctrl *ctrl = priv->ctrl; in rockchip_set_drive_perpin() local
354 struct rockchip_pin_ctrl *ctrl = priv->ctrl; in rockchip_set_pull() local
369 struct rockchip_pin_ctrl *ctrl = priv->ctrl; in rockchip_set_schmitt() local
451 struct rockchip_pin_ctrl *ctrl = priv->ctrl; in rockchip_pinctrl_set_state() local
637 return ctrl; in rockchip_pinctrl_get_soc_data()
[all …]
/drivers/video/nexell/
A Ds5pxx18_dp.c77 swap_rb = ctrl->swap_RB; in dp_control_setup()
78 yc_order = ctrl->yc_order; in dp_control_setup()
80 vclk_invert = ctrl->clk_inv_lv0 | ctrl->clk_inv_lv1; in dp_control_setup()
85 rgb_pvd = ctrl->d_rgb_pvd; in dp_control_setup()
91 de_cp2 = ctrl->d_de_cp2; in dp_control_setup()
95 ctrl->ev_start_offset != 0 || ctrl->ev_end_offset != 0) { in dp_control_setup()
97 v_veo = ctrl->vs_end_offset; in dp_control_setup()
99 e_veo = ctrl->ev_end_offset; in dp_control_setup()
129 6 : ctrl->clk_src_lv0); in dp_control_setup()
174 ctrl->clk_src_lv0, ctrl->clk_div_lv0, ctrl->clk_inv_lv0, in dp_control_setup()
[all …]
A Ds5pxx18_dp_hdmi.c121 struct dp_ctrl_info *ctrl) in hdmi_get_vsync() argument
154 ctrl->clk_src_lv0 = 4; in hdmi_get_vsync()
155 ctrl->clk_div_lv0 = 1; in hdmi_get_vsync()
156 ctrl->clk_src_lv1 = 7; in hdmi_get_vsync()
157 ctrl->clk_div_lv1 = 1; in hdmi_get_vsync()
162 ctrl->d_rgb_pvd = 0; in hdmi_get_vsync()
163 ctrl->d_hsync_cp1 = 0; in hdmi_get_vsync()
164 ctrl->d_vsync_fram = 0; in hdmi_get_vsync()
165 ctrl->d_de_cp2 = 7; in hdmi_get_vsync()
170 ctrl->vs_end_offset = 0; in hdmi_get_vsync()
[all …]
/drivers/video/
A Dnexell_display.c91 ctrl->vs_start_offset = in nx_display_parse_dp_ctrl()
109 ctrl->clk_src_lv0, ctrl->clk_div_lv0, in nx_display_parse_dp_ctrl()
110 ctrl->clk_src_lv1, ctrl->clk_div_lv1); in nx_display_parse_dp_ctrl()
112 ctrl->out_format, ctrl->invert_field, in nx_display_parse_dp_ctrl()
113 ctrl->swap_RB, ctrl->yc_order); in nx_display_parse_dp_ctrl()
115 ctrl->delay_mask, ctrl->d_rgb_pvd, in nx_display_parse_dp_ctrl()
116 ctrl->d_hsync_cp1, ctrl->d_vsync_fram, ctrl->d_de_cp2); in nx_display_parse_dp_ctrl()
118 ctrl->vs_start_offset, ctrl->vs_end_offset, in nx_display_parse_dp_ctrl()
119 ctrl->ev_start_offset, ctrl->ev_end_offset); in nx_display_parse_dp_ctrl()
121 ctrl->vck_select, ctrl->clk_inv_lv0, ctrl->clk_delay_lv0, in nx_display_parse_dp_ctrl()
[all …]
/drivers/pwm/
A Drk_pwm.c62 u32 ctrl; in rk_pwm_set_config() local
66 ctrl = readl(priv->base + regs->ctrl); in rk_pwm_set_config()
72 ctrl |= PWM_LOCK; in rk_pwm_set_config()
73 writel(ctrl, priv->base + regs->ctrl); in rk_pwm_set_config()
96 writel(ctrl, priv->base + regs->ctrl); in rk_pwm_set_config()
107 u32 ctrl; in rk_pwm_set_enable() local
111 ctrl = readl(priv->base + regs->ctrl); in rk_pwm_set_enable()
119 writel(ctrl, priv->base + regs->ctrl); in rk_pwm_set_enable()
165 .ctrl = 0x0c,
179 .ctrl = 0x0c,
[all …]
/drivers/clk/ti/
A Dclk-k3-pll.c95 u32 ctrl; in ti_pll_clk_disable() local
99 if ((ctrl & PLL_16FFT_CTRL_PLL_EN)) { in ti_pll_clk_disable()
100 ctrl &= ~PLL_16FFT_CTRL_PLL_EN; in ti_pll_clk_disable()
113 u32 ctrl; in ti_pll_clk_enable() local
116 ctrl |= PLL_16FFT_CTRL_PLL_EN; in ti_pll_clk_enable()
296 u32 ctrl; in ti_pll_clk_get_rate() local
325 u32 ctrl; in ti_pll_clk_is_bypass() local
336 u32 ctrl; in ti_pll_clk_bypass() local
340 ctrl |= PLL_16FFT_CTRL_BYPASS_EN; in ti_pll_clk_bypass()
342 ctrl &= ~PLL_16FFT_CTRL_BYPASS_EN; in ti_pll_clk_bypass()
[all …]
/drivers/sound/
A Dtegra_i2s.c29 clrsetbits_le32(&regs->ctrl, I2S_CTRL_XFER_EN_TX, in tegra_i2s_transmit_enable()
37 u32 ctrl = readl(&regs->ctrl); in i2s_tx_init() local
40 ctrl &= ~(I2S_CTRL_FRAME_FORMAT_MASK | I2S_CTRL_LRCK_MASK); in i2s_tx_init()
41 ctrl |= I2S_CTRL_FRAME_FORMAT_LRCK; in i2s_tx_init()
42 ctrl |= I2S_CTRL_LRCK_L_LOW; in i2s_tx_init()
45 ctrl &= ~(I2S_CTRL_XFER_EN_TX | I2S_CTRL_XFER_EN_RX); in i2s_tx_init()
48 ctrl |= I2S_CTRL_MASTER_ENABLE; in i2s_tx_init()
51 ctrl &= ~I2S_CTRL_BIT_SIZE_MASK; in i2s_tx_init()
52 ctrl |= audio_bits << I2S_CTRL_BIT_SIZE_SHIFT; in i2s_tx_init()
53 writel(ctrl, &regs->ctrl); in i2s_tx_init()
/drivers/fpga/
A Dsocfpga_gen5.c22 clrsetbits_le32(&fpgamgr_regs->ctrl, in fpgamgr_set_cd_ratio()
42 setbits_le32(&fpgamgr_regs->ctrl, in fpgamgr_program_init()
57 clrbits_le32(&fpgamgr_regs->ctrl, in fpgamgr_program_init()
73 clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCE_MASK); in fpgamgr_program_init()
76 setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK); in fpgamgr_program_init()
79 setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK); in fpgamgr_program_init()
94 clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK); in fpgamgr_program_init()
112 setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK); in fpgamgr_program_init()
133 clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK); in fpgamgr_program_poll_cd()
181 clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK); in fpgamgr_program_poll_usermode()
/drivers/usb/gadget/
A Df_dfu.c271 switch (ctrl->bRequest) { in state_app_idle()
298 switch (ctrl->bRequest) { in state_app_detach()
320 u16 len = le16_to_cpu(ctrl->wLength); in state_dfu_idle()
325 switch (ctrl->bRequest) { in state_dfu_idle()
389 switch (ctrl->bRequest) { in state_dfu_dnload_sync()
412 switch (ctrl->bRequest) { in state_dfu_dnbusy()
436 switch (ctrl->bRequest) { in state_dfu_dnload_idle()
470 switch (ctrl->bRequest) { in state_dfu_manifest_sync()
497 switch (ctrl->bRequest) { in state_dfu_manifest()
527 switch (ctrl->bRequest) { in state_dfu_upload_idle()
[all …]
/drivers/rtc/
A Drx8010sj.c150 u8 ctrl[2]; in rx8010sj_rtc_init() local
175 ctrl[i] = ret; in rx8010sj_rtc_init()
178 if (ctrl[0] & RX8010_FLAG_VLF) in rx8010sj_rtc_init()
181 if (ctrl[0] & RX8010_FLAG_AF) { in rx8010sj_rtc_init()
186 if (ctrl[0] & RX8010_FLAG_TF) in rx8010sj_rtc_init()
189 if (ctrl[0] & RX8010_FLAG_UF) in rx8010sj_rtc_init()
253 int ctrl, flagreg; in rx8010sj_rtc_set() local
262 if (ctrl < 0) in rx8010sj_rtc_set()
263 return ctrl; in rx8010sj_rtc_set()
286 if (ctrl < 0) in rx8010sj_rtc_set()
[all …]
/drivers/usb/dwc3/
A Dep0.c75 trb->ctrl = type; in dwc3_ep0_start_trans()
77 trb->ctrl |= (DWC3_TRB_CTRL_HWO in dwc3_ep0_start_trans()
81 trb->ctrl |= DWC3_TRB_CTRL_CHN; in dwc3_ep0_start_trans()
83 trb->ctrl |= (DWC3_TRB_CTRL_IOC in dwc3_ep0_start_trans()
332 struct usb_ctrlrequest *ctrl) in dwc3_ep0_handle_status() argument
400 wValue = le16_to_cpu(ctrl->wValue); in dwc3_ep0_handle_feature()
505 addr = le16_to_cpu(ctrl->wValue); in dwc3_ep0_set_address()
547 cfg = le16_to_cpu(ctrl->wValue); in dwc3_ep0_set_config()
697 switch (ctrl->bRequest) { in dwc3_ep0_std_request()
745 dwc3_invalidate_cache((uintptr_t)ctrl, sizeof(*ctrl)); in dwc3_ep0_inspect_setup()
[all …]
/drivers/net/
A Daspeed_mdio.c48 u32 ctrl; in aspeed_mdio_read() local
55 ctrl = ASPEED_MDIO_CTRL_FIRE in aspeed_mdio_read()
61 writel(ctrl, priv->base + ASPEED_MDIO_CTRL); in aspeed_mdio_read()
76 u32 ctrl; in aspeed_mdio_write() local
81 ctrl = ASPEED_MDIO_CTRL_FIRE in aspeed_mdio_write()
88 writel(ctrl, priv->base + ASPEED_MDIO_CTRL); in aspeed_mdio_write()
90 return readl_poll_timeout(priv->base + ASPEED_MDIO_CTRL, ctrl, in aspeed_mdio_write()
91 !(ctrl & ASPEED_MDIO_CTRL_FIRE), in aspeed_mdio_write()
/drivers/nvme/
A Dnvme_show.c108 struct nvme_id_ctrl *ctrl; in nvme_print_info() local
112 ctrl = memalign(dev->page_size, sizeof(struct nvme_id_ctrl)); in nvme_print_info()
113 if (!ctrl) in nvme_print_info()
116 if (nvme_identify(dev, 0, 1, (dma_addr_t)(long)ctrl)) { in nvme_print_info()
121 print_optional_admin_cmd(le16_to_cpu(ctrl->oacs), ns->devnum); in nvme_print_info()
122 print_optional_nvm_cmd(le16_to_cpu(ctrl->oncs), ns->devnum); in nvme_print_info()
123 print_format_nvme_attributes(ctrl->fna, ns->devnum); in nvme_print_info()
143 free(ctrl); in nvme_print_info()
/drivers/video/sunxi/
A Dsunxi_dw_hdmi.c36 u32 ctrl; member
75 writel(0, &phy->ctrl); in sunxi_dw_hdmi_phy_init()
76 setbits_le32(&phy->ctrl, BIT(0)); in sunxi_dw_hdmi_phy_init()
78 setbits_le32(&phy->ctrl, BIT(16)); in sunxi_dw_hdmi_phy_init()
79 setbits_le32(&phy->ctrl, BIT(1)); in sunxi_dw_hdmi_phy_init()
81 setbits_le32(&phy->ctrl, BIT(2)); in sunxi_dw_hdmi_phy_init()
83 setbits_le32(&phy->ctrl, BIT(3)); in sunxi_dw_hdmi_phy_init()
88 setbits_le32(&phy->ctrl, 7 << 4); in sunxi_dw_hdmi_phy_init()
100 setbits_le32(&phy->ctrl, BIT(7)); in sunxi_dw_hdmi_phy_init()
111 writel(0x01FF0F7F, &phy->ctrl); in sunxi_dw_hdmi_phy_init()
[all …]
/drivers/mmc/
A Diproc_sdhci.c146 u32 ctrl; in sdhci_iproc_set_ios_post() local
149 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_iproc_set_ios_post()
150 ctrl |= SDHCI_CTRL_VDD_180; in sdhci_iproc_set_ios_post()
151 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); in sdhci_iproc_set_ios_post()
160 u32 ctrl; in sdhci_start_tuning() local
162 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_start_tuning()
163 ctrl |= SDHCI_CTRL_EXEC_TUNING; in sdhci_start_tuning()
164 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); in sdhci_start_tuning()
182 u32 ctrl; in sdhci_iproc_execute_tuning() local
211 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_iproc_execute_tuning()
[all …]

Completed in 1180 milliseconds

1234567