| /drivers/ddr/fsl/ |
| A D | ctrl_regs.c | 87 const unsigned int ctrl_num) in compute_cas_write_latency() argument
121 const unsigned int ctrl_num) in compute_cas_write_latency() argument
323 unsigned int data_rate = get_ddr_freq(ctrl_num); in set_timing_cfg_0()
368 ip_rev = fsl_ddr_get_version(ctrl_num); in set_timing_cfg_0()
376 picos_to_mclk(ctrl_num, 15000)); in set_timing_cfg_0()
574 if (fsl_ddr_get_version(ctrl_num) <= 0x40400) in set_timing_cfg_1()
676 wr_lat = compute_cas_write_latency(ctrl_num); in set_timing_cfg_2()
680 rd_to_pre = picos_to_mclk(ctrl_num, 7500); in set_timing_cfg_2()
712 four_act = picos_to_mclk(ctrl_num, in set_timing_cfg_2()
923 slow = get_ddr_freq(ctrl_num) < 1249000000; in set_ddr_sdram_cfg_2()
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| A D | util.c | 31 u32 fsl_ddr_get_version(unsigned int ctrl_num) in fsl_ddr_get_version() argument
36 switch (ctrl_num) { in fsl_ddr_get_version()
56 printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num); in fsl_ddr_get_version()
73 unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num) in get_memory_clk_period_ps() argument
75 unsigned int data_rate = get_ddr_freq(ctrl_num); in get_memory_clk_period_ps()
95 unsigned long data_rate = get_ddr_freq(ctrl_num); in picos_to_mclk()
121 unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk) in mclk_to_picos() argument
123 return get_memory_clk_period_ps(ctrl_num) * mclk; in mclk_to_picos()
130 unsigned int ctrl_num) in __fsl_ddr_set_lawbar() argument
149 printf("%s: ERROR (ctrl #%d, TRGT ID=%x)\n", __func__, ctrl_num, in __fsl_ddr_set_lawbar()
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| A D | options.c | 32 unsigned int ctrl_num) in fsl_ddr_board_options() argument
750 unsigned int ctrl_num) in populate_memctl_options() argument
1125 ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ? in populate_memctl_options()
1228 "interleaving disabled!\n", ctrl_num); in populate_memctl_options()
1239 "interleaving disabled!\n", ctrl_num); in populate_memctl_options()
1245 "interleaving disabled!\n", ctrl_num); in populate_memctl_options()
1254 "interleaving disabled!\n", ctrl_num); in populate_memctl_options()
1278 "interleaving disabled!\n", ctrl_num); in populate_memctl_options()
1285 "interleaving disabled!\n", ctrl_num); in populate_memctl_options()
1309 ddr_freq = get_ddr_freq(ctrl_num) / 1000000; in populate_memctl_options()
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| A D | lc_common_dimm_params.c | 15 compute_cas_latency(const unsigned int ctrl_num, in compute_cas_latency() argument
25 unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); in compute_cas_latency()
80 compute_cas_latency(const unsigned int ctrl_num, in compute_cas_latency() argument
86 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); in compute_cas_latency()
220 compute_lowest_common_dimm_parameters(const unsigned int ctrl_num, in compute_lowest_common_dimm_parameters() argument
458 if (compute_cas_latency(ctrl_num, dimm_params, in compute_lowest_common_dimm_parameters()
535 (picos_to_mclk(ctrl_num, trcd_ps) > in compute_lowest_common_dimm_parameters()
537 additive_latency = picos_to_mclk(ctrl_num, trcd_ps) - in compute_lowest_common_dimm_parameters()
539 if (mclk_to_picos(ctrl_num, additive_latency) > trcd_ps) { in compute_lowest_common_dimm_parameters()
540 additive_latency = picos_to_mclk(ctrl_num, trcd_ps); in compute_lowest_common_dimm_parameters()
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| A D | ddr1_dimm_params.c | 221 unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num, in ddr_compute_dimm_parameters() argument
304 get_memory_clk_period_ps(ctrl_num)); in ddr_compute_dimm_parameters()
311 pdimm->twr_ps = mclk_to_picos(ctrl_num, 3); in ddr_compute_dimm_parameters()
312 pdimm->twtr_ps = mclk_to_picos(ctrl_num, 1); in ddr_compute_dimm_parameters()
327 pdimm->trtp_ps = mclk_to_picos(ctrl_num, 2); /* By the book. */ in ddr_compute_dimm_parameters()
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| A D | fsl_ddr_gen4.c | 55 unsigned int ctrl_num, int step) in fsl_ddr_set_memctl_regs() argument
87 switch (ctrl_num) { in fsl_ddr_set_memctl_regs()
272 if (fsl_ddr_get_version(ctrl_num) == 0x50200) { in fsl_ddr_set_memctl_regs()
281 } else if (fsl_ddr_get_version(ctrl_num) == 0x50201) { in fsl_ddr_set_memctl_regs()
307 temp32 = get_ddr_freq(ctrl_num) / 1000000; in fsl_ddr_set_memctl_regs()
372 ctrl_num, ddr_in32(&ddr->debug[1])); in fsl_ddr_set_memctl_regs()
377 if (fsl_ddr_get_version(ctrl_num) == 0x50200) { in fsl_ddr_set_memctl_regs()
422 ctrl_num, ddr_in32(&ddr->debug[1])); in fsl_ddr_set_memctl_regs()
478 ddr_freq = get_ddr_freq(ctrl_num) / 1000000; in fsl_ddr_set_memctl_regs()
614 ctrl_num); in fsl_ddr_set_memctl_regs()
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| A D | mpc85xx_ddr_gen1.c | 17 unsigned int ctrl_num, int step) in fsl_ddr_set_memctl_regs() argument
23 if (ctrl_num != 0) { in fsl_ddr_set_memctl_regs()
24 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); in fsl_ddr_set_memctl_regs()
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| A D | mpc85xx_ddr_gen2.c | 17 unsigned int ctrl_num, int step) in fsl_ddr_set_memctl_regs() argument
28 if (ctrl_num) { in fsl_ddr_set_memctl_regs()
29 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); in fsl_ddr_set_memctl_regs()
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| A D | main.c | 45 unsigned int ctrl_num);
211 __weak void update_spd_address(unsigned int ctrl_num, in update_spd_address() argument
218 unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl) in fsl_ddr_get_spd() argument
223 if (ctrl_num >= CONFIG_SYS_NUM_DDR_CTLRS) { in fsl_ddr_get_spd()
224 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); in fsl_ddr_get_spd()
229 i2c_address = spd_i2c_addr[ctrl_num][i]; in fsl_ddr_get_spd()
230 update_spd_address(ctrl_num, i, &i2c_address); in fsl_ddr_get_spd()
236 unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl) in fsl_ddr_get_spd() argument
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| A D | arm_ddr_gen3.c | 32 unsigned int ctrl_num, int step) in fsl_ddr_set_memctl_regs() argument
40 switch (ctrl_num) { in fsl_ddr_set_memctl_regs()
60 printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num); in fsl_ddr_set_memctl_regs()
226 (get_ddr_freq(ctrl_num) >> 20)) << 1; in fsl_ddr_set_memctl_regs()
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| A D | interactive.c | 137 unsigned int ctrl_num, in fsl_ddr_spd_edit() argument
152 unsigned int ctrl_num, in lowest_common_dimm_parameters_edit() argument
219 unsigned int ctrl_num, in fsl_ddr_dimm_parameters_edit() argument
697 unsigned int ctrl_num, in fsl_ddr_regs_edit() argument
785 ctrl_num, regname, value_str); in fsl_ddr_regs_edit()
2092 unsigned int ctrl_num; in fsl_ddr_interactive() local
2162 ctrl_num = __ilog2(ctlr_mask); in fsl_ddr_interactive()
2176 ctrl_num, in fsl_ddr_interactive()
2186 pinfo, ctrl_num, dimm_num, in fsl_ddr_interactive()
2193 ctrl_num, p_element, p_value); in fsl_ddr_interactive()
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| A D | mpc85xx_ddr_gen3.c | 28 unsigned int ctrl_num, int step) in fsl_ddr_set_memctl_regs() argument
54 switch (ctrl_num) { in fsl_ddr_set_memctl_regs()
74 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); in fsl_ddr_set_memctl_regs()
379 ddr_freq = get_ddr_freq(ctrl_num) / 1000000; in fsl_ddr_set_memctl_regs()
478 (get_ddr_freq(ctrl_num) >> 20)) << 1; in fsl_ddr_set_memctl_regs()
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| A D | ddr2_dimm_params.c | 205 unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num, in ddr_compute_dimm_parameters() argument
304 get_memory_clk_period_ps(ctrl_num)); in ddr_compute_dimm_parameters()
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| A D | ddr4_dimm_params.c | 130 unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num, in ddr_compute_dimm_parameters() argument
148 ctrl_num, dimm_number); in ddr_compute_dimm_parameters()
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| A D | ddr3_dimm_params.c | 84 unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num, in ddr_compute_dimm_parameters() argument
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