Searched refs:cwl (Results 1 – 9 of 9) sorted by relevance
| /drivers/ddr/marvell/a38x/ |
| A D | mv_ddr_topology.c | 26 unsigned int cwl; in mv_ddr_cwl_calc() local
29 cwl = 9; in mv_ddr_cwl_calc()
31 cwl = 10; in mv_ddr_cwl_calc()
33 cwl = 11; in mv_ddr_cwl_calc()
35 cwl = 12; in mv_ddr_cwl_calc()
37 cwl = 14; in mv_ddr_cwl_calc()
39 cwl = 16; in mv_ddr_cwl_calc()
41 cwl = 0; in mv_ddr_cwl_calc()
43 return cwl; in mv_ddr_cwl_calc()
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| A D | mv_ddr4_mpr_pda_if.c | 43 u32 cl, cwl; in mv_ddr4_mode_regs_init() local
64 cwl = tm->interface_params[if_id].cas_wl; in mv_ddr4_mode_regs_init()
112 val = g_rtt_wr | (0x0 << 12) | (cwl_mask_table[cwl] << 3); in mv_ddr4_mode_regs_init()
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| /drivers/ddr/fsl/ |
| A D | ctrl_regs.c | 92 cwl = 9; in compute_cas_write_latency()
94 cwl = 10; in compute_cas_write_latency()
96 cwl = 11; in compute_cas_write_latency()
98 cwl = 12; in compute_cas_write_latency()
100 cwl = 14; in compute_cas_write_latency()
102 cwl = 16; in compute_cas_write_latency()
127 cwl = 5; in compute_cas_write_latency()
129 cwl = 6; in compute_cas_write_latency()
131 cwl = 7; in compute_cas_write_latency()
133 cwl = 8; in compute_cas_write_latency()
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| /drivers/ddr/marvell/axp/ |
| A D | ddr3_spd.c | 587 u32 reg, tmp, cwl; local
1100 cwl = 5; /* CWL = 5 */
1102 cwl = 6; /* CWL = 6 */
1104 cwl = 7; /* CWL = 7 */
1106 cwl = 8; /* CWL = 8 */
1108 cwl = 9; /* CWL = 9 */
1110 cwl = 10; /* CWL = 10 */
1112 cwl = 11; /* CWL = 11 */
1114 cwl = 12; /* CWL = 12 */
1116 cwl = 12; /* CWL = 12 */
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| A D | ddr3_dfs.c | 998 reg |= (((dram_info->cwl) & REG_DFS_CWL_NEXT_STATE_MASK) << in ddr3_dfs_low_2_high()
1184 reg |= ((dram_info->cwl) << REG_DDR3_MR2_CWL_OFFS); in ddr3_dfs_low_2_high()
1496 reg |= dram_info->cwl << REG_DDR3_MR2_CWL_OFFS; in ddr3_dfs_low_2_high()
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| A D | ddr3_hw_training.h | 268 u32 cwl; member
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| A D | ddr3_hw_training.c | 146 dram_info.cwl = reg; in ddr3_hw_training()
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| /drivers/ram/octeon/ |
| A D | octeon3_lmc.c | 3157 mp0.s.cwl = 0; in lmc_modereg_params0()
3159 mp0.s.cwl = 1; in lmc_modereg_params0()
3161 mp0.s.cwl = 2; in lmc_modereg_params0()
3163 mp0.s.cwl = 3; in lmc_modereg_params0()
3165 mp0.s.cwl = 4; in lmc_modereg_params0()
3167 mp0.s.cwl = 5; in lmc_modereg_params0()
3169 mp0.s.cwl = 6; in lmc_modereg_params0()
3171 mp0.s.cwl = 7; in lmc_modereg_params0()
3180 mp0.s.cwl + 9 in lmc_modereg_params0()
3181 + ((mp0.s.cwl > 2) ? (mp0.s.cwl - 3) * 2 : 0), mp0.s.cwl); in lmc_modereg_params0()
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| /drivers/ram/rockchip/ |
| A D | sdram_rv1126.c | 1789 u32 mr_tmp, cl, cwl, phy_fsp, offset = 0; in data_training_wr() local
1795 cwl = readl(PHY_REG(phy_base, offset + 2)); in data_training_wr()
1883 clrsetbits_le32(PHY_REG(phy_base, offset + 2), 0x1f, cwl); in data_training_wr()
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