Searched refs:cycle (Results 1 – 8 of 8) sorted by relevance
| /drivers/mfd/ |
| A D | atmel-smc.c | 233 conf->cycle &= ~GENMASK(shift + 15, shift); in atmel_smc_cs_conf_set_cycle()
234 conf->cycle |= val << shift; in atmel_smc_cs_conf_set_cycle()
254 regmap_write(regmap, ATMEL_SMC_CYCLE(cs), conf->cycle); in atmel_smc_cs_conf_apply()
275 regmap_write(regmap, ATMEL_HSMC_CYCLE(layout, cs), conf->cycle); in atmel_hsmc_cs_conf_apply()
295 regmap_read(regmap, ATMEL_SMC_CYCLE(cs), &conf->cycle); in atmel_smc_cs_conf_get()
316 regmap_read(regmap, ATMEL_HSMC_CYCLE(layout, cs), &conf->cycle); in atmel_hsmc_cs_conf_get()
|
| /drivers/pwm/ |
| A D | Kconfig | 6 control over the duty cycle (high and low time) of the signal. This
18 and duty cycle. It provides 16 channels which can be independently
48 supports a programmable period and duty cycle. A 32-bit counter is
62 programmable period and duty cycle for 2 independant channels.
69 programmable period and duty cycle.
76 programmable period and duty cycle. A 32-bit counter is used.
104 four channels with a programmable period and duty cycle. Only a
105 32KHz clock is supported by the driver but the duty cycle is
121 programmable period and duty cycle. A 16-bit counter is used.
|
| /drivers/spi/ |
| A D | ich.c | 526 int cycle; in ich_spi_exec_op_hwseq() local
537 cycle = HSFSTS_CYCLE_RDID; in ich_spi_exec_op_hwseq()
540 cycle = HSFSTS_CYCLE_READ; in ich_spi_exec_op_hwseq()
543 cycle = HSFSTS_CYCLE_WRITE; in ich_spi_exec_op_hwseq()
549 cycle = HSFSTS_CYCLE_WR_STATUS; in ich_spi_exec_op_hwseq()
552 cycle = HSFSTS_CYCLE_RD_STATUS; in ich_spi_exec_op_hwseq()
557 cycle = HSFSTS_CYCLE_4K_ERASE; in ich_spi_exec_op_hwseq()
558 ret = exec_sync_hwseq_xfer(regs, cycle, offset, 0); in ich_spi_exec_op_hwseq()
575 ret = exec_sync_hwseq_xfer(regs, cycle, offset, xfer_len); in ich_spi_exec_op_hwseq()
|
| /drivers/mtd/nand/raw/atmel/ |
| A D | pmecc.h | 56 u32 cycle; member
|
| /drivers/clk/at91/ |
| A D | clk-main.c | 234 unsigned int cycle = DIV_ROUND_UP(USEC_PER_SEC, SLOW_CLOCK_FREQ); in clk_main_probe_frequency() local
241 udelay(cycle); in clk_main_probe_frequency()
|
| /drivers/mtd/ubi/ |
| A D | Kconfig | 48 other flashes which have eraseblock life-cycle 100000 or more.
50 life-cycle less than 10000, the threshold should be lessened (e.g.,
|
| /drivers/video/ |
| A D | dw_mipi_dsi.c | 184 #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8) argument
|
| /drivers/pinctrl/ |
| A D | Kconfig | 209 one-half of peripheral clock cycle and a debouncing filter providing
|
Completed in 26 milliseconds