Searched refs:cycles (Results 1 – 10 of 10) sorted by relevance
| /drivers/ram/k3-ddrss/ |
| A D | lpddr4.c | 747 readpdwakeup(fspnum, ctlregbase, cycles); in lpddr4_readlpiwakeuptime()
749 readsrshortwakeup(fspnum, ctlregbase, cycles); in lpddr4_readlpiwakeuptime()
751 readsrlongwakeup(fspnum, ctlregbase, cycles); in lpddr4_readlpiwakeuptime()
753 readsrlonggatewakeup(fspnum, ctlregbase, cycles); in lpddr4_readlpiwakeuptime()
755 readsrdpshortwakeup(fspnum, ctlregbase, cycles); in lpddr4_readlpiwakeuptime()
757 readsrdplongwakeup(fspnum, ctlregbase, cycles); in lpddr4_readlpiwakeuptime()
888 writepdwakeup(fspnum, ctlregbase, cycles); in lpddr4_writelpiwakeuptime()
890 writesrshortwakeup(fspnum, ctlregbase, cycles); in lpddr4_writelpiwakeuptime()
892 writesrlongwakeup(fspnum, ctlregbase, cycles); in lpddr4_writelpiwakeuptime()
898 writesrdplongwakeup(fspnum, ctlregbase, cycles); in lpddr4_writelpiwakeuptime()
[all …]
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| A D | lpddr4_obj_if.h | 59 …ata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, u32 *cycles);
61 …d, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles);
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| A D | lpddr4_if.h | 122 …ata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, u32 *cycles);
124 …d, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles);
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| A D | lpddr4_sanity.h | 30 …d, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles);
254 …pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles) in lpddr4_sanityfunction19() argument
262 } else if (cycles == NULL) { in lpddr4_sanityfunction19()
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| /drivers/pwm/ |
| A D | pwm-at91.c | 41 u64 cycles = period_ns; in at91_pwm_calculate_cprd_and_pres() local
45 cycles *= clkrate; in at91_pwm_calculate_cprd_and_pres()
46 do_div(cycles, NSEC_PER_SEC); in at91_pwm_calculate_cprd_and_pres()
53 shift = fls(cycles) - PERIOD_BITS; in at91_pwm_calculate_cprd_and_pres()
59 cycles >>= *pres; in at91_pwm_calculate_cprd_and_pres()
64 *cprd = cycles; in at91_pwm_calculate_cprd_and_pres()
73 u64 cycles = duty_ns; in at91_pwm_calculate_cdty() local
75 cycles *= clkrate; in at91_pwm_calculate_cdty()
76 do_div(cycles, NSEC_PER_SEC); in at91_pwm_calculate_cdty()
77 cycles >>= pres; in at91_pwm_calculate_cdty()
[all …]
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| /drivers/watchdog/ |
| A D | renesas_wdt.c | 48 static void rwdt_wait_cycles(struct rwdt_priv *priv, unsigned int cycles) in rwdt_wait_cycles() argument
52 delay = DIV_ROUND_UP(cycles * 1000000, priv->clk_rate); in rwdt_wait_cycles()
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| /drivers/clk/at91/ |
| A D | clk-main.c | 233 unsigned int cycles = 16; in clk_main_probe_frequency() local
237 while (cycles--) { in clk_main_probe_frequency()
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| /drivers/bootcount/ |
| A D | Kconfig | 179 int "Maximum number of reboot cycles allowed"
182 Set the Maximum number of reboot cycles allowed without the boot
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| /drivers/ram/octeon/ |
| A D | octeon_ddr.c | 1454 static void octeon_ipd_delay_cycles(u64 cycles) in octeon_ipd_delay_cycles() argument
1458 while (start + cycles > csr_rd(CVMX_IPD_CLK_COUNT)) in octeon_ipd_delay_cycles()
1462 static void octeon_ipd_delay_cycles_o3(u64 cycles) in octeon_ipd_delay_cycles_o3() argument
1466 while (start + cycles > csr_rd(CVMX_FPA_CLK_COUNT)) in octeon_ipd_delay_cycles_o3()
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| /drivers/mtd/nand/raw/ |
| A D | Kconfig | 702 bool "Wait 5 address cycles during NAND commands"
707 Some controllers require waiting for 5 address cycles when issuing
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