Searched refs:data_read (Results 1 – 10 of 10) sorted by relevance
| /drivers/ddr/marvell/a38x/old/ |
| A D | ddr3_training_leveling.c | 300 data = data_read[if_id]; in ddr3_tip_dynamic_read_leveling()
348 [bus_num], data_read, in ddr3_tip_dynamic_read_leveling()
534 u32 data_read[MAX_INTERFACE_NUM]; in ddr3_tip_dynamic_per_bit_read_leveling() local
699 data = data_read[if_id]; in ddr3_tip_dynamic_per_bit_read_leveling()
760 data_read, in ddr3_tip_dynamic_per_bit_read_leveling()
763 (data_read in ddr3_tip_dynamic_per_bit_read_leveling()
766 ((data_read in ddr3_tip_dynamic_per_bit_read_leveling()
1103 data_read, (1 << 2))); in ddr3_tip_dynamic_write_leveling()
1104 reg_data = data_read[if_id]; in ddr3_tip_dynamic_write_leveling()
1125 [bus_cnt], data_read, in ddr3_tip_dynamic_write_leveling()
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| A D | ddr3_training.c | 316 u32 data_read[MAX_INTERFACE_NUM]; in hws_ddr3_tip_init_controller() local
617 DRAM_PHY_CONFIGURATION, data_read, 0x30)); in hws_ddr3_tip_init_controller()
619 (data_read[if_id] == 0) ? (1 << 11) : 0; in hws_ddr3_tip_init_controller()
989 u32 data_read[MAX_INTERFACE_NUM]; in ddr3_tip_bus_read() local
1003 PHY_REG_FILE_ACCESS, data_read, in ddr3_tip_bus_read()
1005 data[bus_index] = (data_read[if_id] & 0xffff); in ddr3_tip_bus_read()
1020 *data = (data_read[if_id] & 0xffff); in ddr3_tip_bus_read()
1092 u32 data_read[MAX_INTERFACE_NUM]; in is_bus_access_done() local
1096 data_read, MASK_ALL_BITS)); in is_bus_access_done()
1097 rd_data = data_read[if_id]; in is_bus_access_done()
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| A D | ddr3_training_hw_algo.c | 52 u32 data_read[MAX_INTERFACE_NUM] = { 0 }; in ddr3_tip_write_additional_odt_setting() local
65 data_read, MASK_ALL_BITS)); in ddr3_tip_write_additional_odt_setting()
66 val = data_read[if_id]; in ddr3_tip_write_additional_odt_setting()
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| A D | ddr3_debug.c | 1498 u32 data_read[MAX_INTERFACE_NUM]; in run_xsb_test() local
1514 data_read)); in run_xsb_test()
1520 data_read, in run_xsb_test()
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| /drivers/ddr/marvell/a38x/ |
| A D | ddr3_training_leveling.c | 223 [bus_num], data_read, in ddr3_tip_dynamic_read_leveling()
408 u32 data_read[MAX_INTERFACE_NUM]; in ddr3_tip_dynamic_per_bit_read_leveling() local
608 data_read, in ddr3_tip_dynamic_per_bit_read_leveling()
611 (data_read in ddr3_tip_dynamic_per_bit_read_leveling()
614 ((data_read in ddr3_tip_dynamic_per_bit_read_leveling()
815 u32 data_read[MAX_INTERFACE_NUM]; in ddr3_tip_dynamic_write_leveling() local
917 reg_data = data_read[0]; in ddr3_tip_dynamic_write_leveling()
930 reg_data = data_read[0]; in ddr3_tip_dynamic_write_leveling()
937 data_read, 0xff); in ddr3_tip_dynamic_write_leveling()
1097 [bus_cnt], data_read, in ddr3_tip_dynamic_write_leveling()
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| A D | ddr3_training_hw_algo.c | 46 u32 data_read[MAX_INTERFACE_NUM] = { 0 }; in ddr3_tip_write_additional_odt_setting() local
60 data_read, MASK_ALL_BITS)); in ddr3_tip_write_additional_odt_setting()
61 val = data_read[if_id]; in ddr3_tip_write_additional_odt_setting()
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| A D | ddr3_debug.c | 1474 u32 data_read[MAX_INTERFACE_NUM]; in run_xsb_test() local
1490 data_read)); in run_xsb_test()
1496 data_read, in run_xsb_test()
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| A D | ddr3_training.c | 373 u32 data_read[MAX_INTERFACE_NUM]; in hws_ddr3_tip_init_controller() local
647 DRAM_PHY_CFG_REG, data_read, 0x30)); in hws_ddr3_tip_init_controller()
649 (data_read[if_id] == 0) ? (1 << 11) : 0; in hws_ddr3_tip_init_controller()
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| A D | mv_ddr4_training_calibration.c | 2319 u32 data_read[MAX_INTERFACE_NUM]; in refresh() local
2320 ddr3_tip_if_read(0, ACCESS_TYPE_UNICAST, 0, ODPG_DATA_CTRL_REG, data_read, MASK_ALL_BITS); in refresh()
2335 ddr3_tip_if_write(0, ACCESS_TYPE_UNICAST, 0, ODPG_DATA_CTRL_REG, data_read[0] , MASK_ALL_BITS); in refresh()
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| /drivers/i2c/ |
| A D | i2c-microchip.c | 216 u8 data_read; in mpfs_i2c_empty_rx() local
219 data_read = readl(bus->base + MPFS_I2C_DATA); in mpfs_i2c_empty_rx()
220 *bus->buf++ = data_read; in mpfs_i2c_empty_rx()
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