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Searched refs:dbi_base (Results 1 – 12 of 12) sorted by relevance

/drivers/pci/
A Dpcie_imx.c109 void __iomem *dbi_base; member
150 ret = pcie_phy_poll_ack(dbi_base, 1); in pcie_phy_wait_ack()
157 ret = pcie_phy_poll_ack(dbi_base, 0); in pcie_phy_wait_ack()
178 ret = pcie_phy_poll_ack(dbi_base, 1); in pcie_phy_read()
188 ret = pcie_phy_poll_ack(dbi_base, 0); in pcie_phy_read()
213 ret = pcie_phy_poll_ack(dbi_base, 1); in pcie_phy_write()
222 ret = pcie_phy_poll_ack(dbi_base, 0); in pcie_phy_write()
351 va_address = priv->dbi_base; in get_bus_address()
661 tmp = readl(priv->dbi_base + 0x18); in imx_pcie_link_up()
663 writel(tmp, priv->dbi_base + 0x18); in imx_pcie_link_up()
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A Dpcie_ecam_synquacer.c183 phys_addr_t dbi_base; member
188 .dbi_base = SYNQUACER_PCI_SEG0_DBI_BASE,
192 .dbi_base = SYNQUACER_PCI_SEG1_DBI_BASE,
204 void *dbi_base; member
346 pcie->dbi_base = map_physmem(synquacer_pci_bases[i].dbi_base, in pci_synquacer_ecam_of_to_plat()
348 if (!pcie->dbi_base) { in pci_synquacer_ecam_of_to_plat()
434 dbi_base + IATU_VIEWPORT_OFF); in pcie_sq_prog_outbound_atu()
490 pci_synquacer_dbi_init(pcie->dbi_base); in pci_synquacer_post_init()
492 or_writel(pcie->dbi_base, PCI_COMMAND, in pci_synquacer_post_init()
499 pcie_sq_prog_outbound_atu(pcie->dbi_base, 0, in pci_synquacer_post_init()
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A Dpcie_dw_common.c22 return (readl(pci->dbi_base + PCIE_LINK_STATUS_REG) & in pcie_dw_get_link_speed()
28 return (readl(pci->dbi_base + PCIE_LINK_STATUS_REG) & in pcie_dw_get_link_width()
41 plc = readl(pci->dbi_base + PCIE_PORT_LINK_CONTROL); in dw_pcie_link_set_max_link_width()
66 writel(plc, pci->dbi_base + PCIE_PORT_LINK_CONTROL); in dw_pcie_link_set_max_link_width()
70 lnkcap = readl(pci->dbi_base + cap + PCI_EXP_LNKCAP); in dw_pcie_link_set_max_link_width()
172 va_address = (uintptr_t)pcie->dbi_base; in set_cfg_address()
329 val = readl(pci->dbi_base + (cap_ptr & ~0x3)); in pcie_dw_find_next_cap()
376 pci->dbi_base + PCI_BASE_ADDRESS_0); in pcie_dw_setup_host()
377 writel(0x0, pci->dbi_base + PCI_BASE_ADDRESS_1); in pcie_dw_setup_host()
384 clrsetbits_le32(pci->dbi_base + PCI_PRIMARY_BUS, in pcie_dw_setup_host()
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A Dpcie_dw_meson.c114 val = readl(priv->dw.dbi_base + PCIE_PORT_LINK_CONTROL); in meson_pcie_configure()
118 writel(val, priv->dw.dbi_base + PCIE_PORT_LINK_CONTROL); in meson_pcie_configure()
225 val = readl(priv->dw.dbi_base + offset + PCI_EXP_DEVCTL); in meson_set_max_payload()
227 writel(val, priv->dw.dbi_base + offset + PCI_EXP_DEVCTL); in meson_set_max_payload()
229 val = readl(priv->dw.dbi_base + offset + PCI_EXP_DEVCTL); in meson_set_max_payload()
231 writel(val, priv->dw.dbi_base + PCI_EXP_DEVCTL); in meson_set_max_payload()
244 val = readl(priv->dw.dbi_base + offset + PCI_EXP_DEVCTL); in meson_set_max_rd_req_size()
246 writel(val, priv->dw.dbi_base + offset + PCI_EXP_DEVCTL); in meson_set_max_rd_req_size()
250 writel(val, priv->dw.dbi_base + PCI_EXP_DEVCTL); in meson_set_max_rd_req_size()
335 priv->dw.dbi_base = dev_read_addr_index_ptr(dev, 0); in meson_pcie_parse_dt()
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A Dpcie_uniphier.c82 void *dbi_base; member
117 priv->dbi_base + PCIE_ATU_VIEWPORT); in pcie_dw_prog_outbound_atu()
119 priv->dbi_base + PCIE_ATU_LOWER_BASE); in pcie_dw_prog_outbound_atu()
121 priv->dbi_base + PCIE_ATU_UPPER_BASE); in pcie_dw_prog_outbound_atu()
123 priv->dbi_base + PCIE_ATU_LIMIT); in pcie_dw_prog_outbound_atu()
125 priv->dbi_base + PCIE_ATU_LOWER_TARGET); in pcie_dw_prog_outbound_atu()
127 priv->dbi_base + PCIE_ATU_UPPER_TARGET); in pcie_dw_prog_outbound_atu()
129 writel(type, priv->dbi_base + PCIE_ATU_CR1); in pcie_dw_prog_outbound_atu()
155 *paddr = (void *)(priv->dbi_base + offset); in uniphier_pcie_conf_address()
299 priv->dbi_base = map_physmem(priv->dbi_res.start, in uniphier_pcie_probe()
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A Dpcie_dw_ti.c87 val = readl(pci->dw.dbi_base + PCIE_LINK_CAPABILITY); in pcie_dw_configure()
90 writel(val, pci->dw.dbi_base + PCIE_LINK_CAPABILITY); in pcie_dw_configure()
92 val = readl(pci->dw.dbi_base + PCIE_LINK_CTL_2); in pcie_dw_configure()
95 writel(val, pci->dw.dbi_base + PCIE_LINK_CTL_2); in pcie_dw_configure()
111 val = readl(pci->dw.dbi_base + PCIE_PORT_DEBUG0); in is_link_up()
219 writew(id & PCIE_VENDORID_MASK, pci->dw.dbi_base + PCI_VENDOR_ID); in pcie_dw_init_id()
220 writew(id >> PCIE_DEVICEID_SHIFT, pci->dw.dbi_base + PCI_DEVICE_ID); in pcie_dw_init_id()
318 pcie->dw.dbi_base = (void *)dev_read_addr_name(dev, "dbics"); in pcie_dw_ti_of_to_plat()
319 if ((fdt_addr_t)pcie->dw.dbi_base == FDT_ADDR_T_NONE) in pcie_dw_ti_of_to_plat()
A Dpci-rcar-gen4.c133 clrbits_le32(rcar->dw.dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL, in rcar_gen4_pcie_speed_change()
136 setbits_le32(rcar->dw.dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL, in rcar_gen4_pcie_speed_change()
140 val = readl(rcar->dw.dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); in rcar_gen4_pcie_speed_change()
158 if (readl(rcar->dw.dbi_base + offset) & mask) in rcar_gen4_pcie_reg_test_bit()
181 writel(RCAR_GEN4_PCIE_FIRMWARE_BASE_ADDR + i, rcar->dw.dbi_base + PRTLGC89); in rcar_gen4_pcie_download_phy_firmware()
182 writel(data, rcar->dw.dbi_base + PRTLGC90); in rcar_gen4_pcie_download_phy_firmware()
196 writel(check_addr[i], rcar->dw.dbi_base + PRTLGC89); in rcar_gen4_pcie_download_phy_firmware()
220 setbits_le32(rcar->dw.dbi_base + PCIE_PORT_FORCE, in rcar_gen4_pcie_ltssm_control()
289 clrsetbits_le32(rcar->dw.dbi_base + PCIE_PORT_LANE_SKEW, in rcar_gen4_pcie_additional_common_init()
507 rcar->dw.dbi_base = (void *)dev_read_addr_name(dev, "dbi"); in rcar_gen4_pcie_of_to_plat()
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A Dpcie_dw_sifive.c265 val = readl(sv->dw.dbi_base + PHY_DEBUG_R1); in pcie_sifive_check_link()
281 val = readl(sv->dw.dbi_base + PCIE_MISC_CONTROL_1); in pcie_sifive_force_gen1()
283 writel(val, sv->dw.dbi_base + PCIE_MISC_CONTROL_1); in pcie_sifive_force_gen1()
286 linkcap = readl(sv->dw.dbi_base + PF0_PCIE_CAP_LINK_CAP); in pcie_sifive_force_gen1()
288 writel(linkcap, sv->dw.dbi_base + PF0_PCIE_CAP_LINK_CAP); in pcie_sifive_force_gen1()
292 writel(val, sv->dw.dbi_base + PCIE_MISC_CONTROL_1); in pcie_sifive_force_gen1()
298 readl(sv->dw.dbi_base + PHY_DEBUG_R0), in pcie_sifive_print_phy_debug()
299 readl(sv->dw.dbi_base + PHY_DEBUG_R1)); in pcie_sifive_print_phy_debug()
315 val = readl(sv->dw.dbi_base + PHY_DEBUG_R1); in pcie_sifive_wait_for_link()
448 sv->dw.dbi_base = get_fdt_addr(dev, "dbi"); in pcie_sifive_of_to_plat()
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A Dpcie_dw_qcom.c176 val = readw(priv->dw.dbi_base + offset + PCI_EXP_LNKSTA); in qcom_pcie_wait_link_up()
195 val = readl(priv->dw.dbi_base + offset + PCI_EXP_LNKCAP); in qcom_pcie_clear_aspm_l0s()
197 writel(val, priv->dw.dbi_base + offset + PCI_EXP_LNKCAP); in qcom_pcie_clear_aspm_l0s()
209 val = readl(priv->dw.dbi_base + offset + PCI_EXP_SLTCAP); in qcom_pcie_clear_hpc()
211 writel(val, priv->dw.dbi_base + offset + PCI_EXP_SLTCAP); in qcom_pcie_clear_hpc()
287 val = readl(priv->dw.dbi_base + PCIE_PORT_LINK_CONTROL); in qcom_pcie_configure()
291 writel(val, priv->dw.dbi_base + PCIE_PORT_LINK_CONTROL); in qcom_pcie_configure()
423 priv->dw.dbi_base = dev_read_addr_name_ptr(dev, "dbi"); in qcom_pcie_parse_dt()
424 if (!priv->dw.dbi_base) in qcom_pcie_parse_dt()
427 dev_dbg(dev, "DBI address is 0x%p\n", priv->dw.dbi_base); in qcom_pcie_parse_dt()
A Dpcie_dw_rockchip.c164 writel(0, pci->dw.dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET + in rk_pcie_configure()
166 writel(0, pci->dw.dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET + in rk_pcie_configure()
169 clrsetbits_le32(pci->dw.dbi_base + PCIE_LINK_CAPABILITY, in rk_pcie_configure()
172 clrsetbits_le32(pci->dw.dbi_base + PCIE_LINK_CTL_2, in rk_pcie_configure()
370 priv->dw.dbi_base = dev_read_addr_index_ptr(dev, 0); in rockchip_pcie_parse_dt()
371 if (!priv->dw.dbi_base) in rockchip_pcie_parse_dt()
374 dev_dbg(dev, "DBI address is 0x%p\n", priv->dw.dbi_base); in rockchip_pcie_parse_dt()
A Dpcie_dw_common.h123 void __iomem *dbi_base; member
157 val = readl(pci->dbi_base + PCIE_MISC_CONTROL_1_OFF); in dw_pcie_dbi_write_enable()
162 writel(val, pci->dbi_base + PCIE_MISC_CONTROL_1_OFF); in dw_pcie_dbi_write_enable()
A Dpcie_dw_imx.c75 clrsetbits_le32(priv->dw.dbi_base + PCIE_LINK_CAPABILITY, in pcie_dw_configure()
101 return readl_poll_sleep_timeout(priv->dw.dbi_base + PCIE_PORT_DEBUG1, in wait_link_up()
263 priv->dw.dbi_base = (void *)dev_read_addr_name(dev, "dbi"); in pcie_dw_imx_of_to_plat()
264 if ((fdt_addr_t)priv->dw.dbi_base == FDT_ADDR_T_NONE) { in pcie_dw_imx_of_to_plat()

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