Searched refs:dc (Results 1 – 10 of 10) sorted by relevance
| /drivers/video/tegra/ |
| A D | dc.c | 60 struct dc_ctlr *dc = priv->dc; in update_window() local
75 writel(val, &dc->win.pos); in update_window()
79 writel(val, &dc->win.size); in update_window()
85 writel(0, &dc->win.h_initial_dda); in update_window()
86 writel(0, &dc->win.v_initial_dda); in update_window()
96 writel(0, &dc->win.buf_stride); in update_window()
105 writel(val, &dc->win.win_opt); in update_window()
116 writel(val, &dc->cmd.state_ctrl); in update_window()
345 basic_init(&priv->dc->cmd); in tegra_display_probe()
554 dc_plat->dc = priv->dc; in tegra_lcd_configure_internal()
[all …]
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| A D | dc-pwm-backlight.c | 34 struct dc_ctlr *dc; /* Display controller regmap */ member
46 struct dc_cmd_reg *cmd = &priv->dc->cmd; in tegra_pwm_backlight_set_brightness()
47 struct dc_com_reg *com = &priv->dc->com; in tegra_pwm_backlight_set_brightness()
106 ofnode dc = ofnode_get_parent(dev_ofnode(dev)); in tegra_pwm_backlight_probe() local
108 priv->dc = (struct dc_ctlr *)ofnode_get_addr(dc); in tegra_pwm_backlight_probe()
109 if (!priv->dc) { in tegra_pwm_backlight_probe()
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| A D | cpu-bridge.c | 25 struct dc_ctlr *dc; member
116 struct dc_disp_reg *disp = &priv->dc->disp; in tegra_cpu_bridge_attach()
117 struct dc_cmd_reg *cmd = &priv->dc->cmd; in tegra_cpu_bridge_attach()
118 struct dc_com_reg *com = &priv->dc->com; in tegra_cpu_bridge_attach()
225 ofnode dc = ofnode_get_parent(remote); in tegra_cpu_bridge_get_links() local
227 priv->dc = (struct dc_ctlr *)ofnode_get_addr(dc); in tegra_cpu_bridge_get_links()
228 if (!priv->dc) { in tegra_cpu_bridge_get_links()
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| A D | hdmi.c | 170 struct dc_ctlr *dc = dc_plat->dc; in tegra_dc_enable_controller() local
173 value = readl(&dc->disp.disp_win_opt); in tegra_dc_enable_controller()
175 writel(value, &dc->disp.disp_win_opt); in tegra_dc_enable_controller()
177 writel(GENERAL_UPDATE, &dc->cmd.state_ctrl); in tegra_dc_enable_controller()
178 writel(GENERAL_ACT_REQ, &dc->cmd.state_ctrl); in tegra_dc_enable_controller()
202 struct dc_ctlr *dc = dc_plat->dc; in tegra_hdmi_encoder_enable() local
222 writel(VSYNC_H_POSITION(1), &dc->disp.disp_timing_opt); in tegra_hdmi_encoder_enable()
224 &dc->disp.disp_color_ctrl); in tegra_hdmi_encoder_enable()
229 writel(H_PULSE2_ENABLE, &dc->disp.disp_signal_opt0); in tegra_hdmi_encoder_enable()
233 writel(value, &dc->disp.h_pulse[H_PULSE2].h_pulse_ctrl); in tegra_hdmi_encoder_enable()
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| A D | Makefile | 4 obj-$(CONFIG_VIDEO_TEGRA) += dc.o
7 obj-$(CONFIG_TEGRA_BACKLIGHT_PWM) += dc-pwm-backlight.o
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| A D | dc.h | 19 struct dc_ctlr *dc; /* Display controller regmap */ member
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| A D | dsi.c | 68 struct dc_ctlr *dc = dc_plat->dc; in tegra_dc_enable_controller() local
71 value = readl(&dc->disp.disp_win_opt); in tegra_dc_enable_controller()
73 writel(value, &dc->disp.disp_win_opt); in tegra_dc_enable_controller()
75 writel(GENERAL_UPDATE, &dc->cmd.state_ctrl); in tegra_dc_enable_controller()
76 writel(GENERAL_ACT_REQ, &dc->cmd.state_ctrl); in tegra_dc_enable_controller()
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| /drivers/spi/ |
| A D | ti_qspi.c | 83 u32 dc; member
108 u32 dc; member
218 cmd | QSPI_WR_SNGL, priv->dc); in ti_qspi_xfer()
313 priv->dc = 0; in ti_qspi_set_mode()
315 priv->dc |= QSPI_CKPHA(0); in ti_qspi_set_mode()
317 priv->dc |= QSPI_CKPOL(0); in ti_qspi_set_mode()
319 priv->dc |= QSPI_CSPOL(0); in ti_qspi_set_mode()
376 writel(priv->dc, &priv->base->dc); in ti_qspi_claim_bus()
380 priv->dc <<= slave_plat->cs[0] * 8; in ti_qspi_claim_bus()
381 writel(priv->dc, &priv->base->dc); in ti_qspi_claim_bus()
[all …]
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| /drivers/video/meson/ |
| A D | meson_registers.h | 1564 #define VPU_RDARB_SLAVE_TO_MASTER_PORT(dc, port) (port << (16 + dc)) argument
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| /drivers/net/ |
| A D | e1000.h | 981 uint64_t dc; member
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