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Searched refs:ddr (Results 1 – 20 of 20) sorted by relevance

/drivers/ddr/fsl/
A Dfsl_ddr_gen4.c58 struct ccsr_ddr __iomem *ddr; in fsl_ddr_set_memctl_regs() local
126 ddr_out32(&ddr->cs0_bnds, in fsl_ddr_set_memctl_regs()
128 ddr_out32(&ddr->cs0_config, in fsl_ddr_set_memctl_regs()
139 ddr_out32(&ddr->cs1_bnds, in fsl_ddr_set_memctl_regs()
149 ddr_out32(&ddr->cs2_bnds, in fsl_ddr_set_memctl_regs()
159 ddr_out32(&ddr->cs3_bnds, in fsl_ddr_set_memctl_regs()
231 ddr_out32(&ddr->sdram_cfg_2, in fsl_ddr_set_memctl_regs()
237 ddr_out32(&ddr->ddr_cdr2, in fsl_ddr_set_memctl_regs()
274 ddr_out32(&ddr->ddr_cdr2, in fsl_ddr_set_memctl_regs()
285 ddr_out32(&ddr->ddr_cdr2, in fsl_ddr_set_memctl_regs()
[all …]
A Dmpc85xx_ddr_gen3.c31 struct ccsr_ddr __iomem *ddr; in fsl_ddr_set_memctl_regs() local
164 out_be32(&ddr->sdram_cfg_2, in fsl_ddr_set_memctl_regs()
170 out_be32(&ddr->ddr_cdr2, in fsl_ddr_set_memctl_regs()
220 out_be32(&ddr->mtcr, 0); in fsl_ddr_set_memctl_regs()
234 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
245 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
254 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
265 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
421 in_be32(&ddr->sdram_cfg_2)); in fsl_ddr_set_memctl_regs()
507 in_be32(&ddr->sdram_cfg_2)); in fsl_ddr_set_memctl_regs()
[all …]
A Darm_ddr_gen3.c35 struct ccsr_ddr __iomem *ddr; in fsl_ddr_set_memctl_regs() local
42 ddr = (void *)CFG_SYS_FSL_DDR_ADDR; in fsl_ddr_set_memctl_regs()
46 ddr = (void *)CFG_SYS_FSL_DDR2_ADDR; in fsl_ddr_set_memctl_regs()
51 ddr = (void *)CFG_SYS_FSL_DDR3_ADDR; in fsl_ddr_set_memctl_regs()
56 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; in fsl_ddr_set_memctl_regs()
68 ddr_out32(&ddr->eor, regs->ddr_eor); in fsl_ddr_set_memctl_regs()
127 ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1); in fsl_ddr_set_memctl_regs()
130 ddr_out32(&ddr->sdram_cfg_2, in fsl_ddr_set_memctl_regs()
136 ddr_out32(&ddr->ddr_cdr2, in fsl_ddr_set_memctl_regs()
144 ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2); in fsl_ddr_set_memctl_regs()
[all …]
A Dctrl_regs.c228 ddr->cs[i].config = (0 in set_csn_config()
441 ddr->timing_cfg_0 = (0 in set_timing_cfg_0()
494 ddr->timing_cfg_3 = (0 in set_timing_cfg_3()
622 ddr->timing_cfg_1 = (0 in set_timing_cfg_1()
715 ddr->timing_cfg_2 = (0 in set_timing_cfg_2()
851 ddr->ddr_sdram_cfg = (0 in set_ddr_sdram_cfg()
1915 ddr->timing_cfg_4 = (0 in set_timing_cfg_4()
1945 ddr->timing_cfg_5 = (0 in set_timing_cfg_5()
1963 ddr->timing_cfg_6 = (0 in set_timing_cfg_6()
2192 ddr->ddr_zq_cntl = (0 in set_ddr_zq_cntl()
[all …]
A Dmpc85xx_ddr_gen2.c20 struct ccsr_ddr __iomem *ddr = in fsl_ddr_set_memctl_regs() local
50 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
51 out_be32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
54 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
55 out_be32(&ddr->cs1_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
58 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
59 out_be32(&ddr->cs2_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
62 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
78 out_be32(&ddr->init_addr, regs->ddr_init_addr); in fsl_ddr_set_memctl_regs()
88 out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg); in fsl_ddr_set_memctl_regs()
[all …]
A Dmpc85xx_ddr_gen1.c20 struct ccsr_ddr __iomem *ddr = in fsl_ddr_set_memctl_regs() local
30 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
31 out_be32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
34 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
35 out_be32(&ddr->cs1_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
38 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
39 out_be32(&ddr->cs2_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
42 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
59 out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg); in fsl_ddr_set_memctl_regs()
73 struct ccsr_ddr __iomem *ddr = in ddr_enable_ecc() local
[all …]
A Dutil.c33 struct ccsr_ddr __iomem *ddr; in fsl_ddr_get_version() local
38 ddr = (void *)CFG_SYS_FSL_DDR_ADDR; in fsl_ddr_get_version()
42 ddr = (void *)CFG_SYS_FSL_DDR2_ADDR; in fsl_ddr_get_version()
47 ddr = (void *)CFG_SYS_FSL_DDR3_ADDR; in fsl_ddr_get_version()
52 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; in fsl_ddr_get_version()
184 struct ccsr_ddr __iomem *ddr = in print_ddr_info() local
352 struct ccsr_ddr __iomem *ddr; in fsl_ddr_sync_memctl_refresh() local
357 ddr = (void *)CFG_SYS_FSL_DDR_ADDR; in fsl_ddr_sync_memctl_refresh()
361 ddr = (void *)CFG_SYS_FSL_DDR2_ADDR; in fsl_ddr_sync_memctl_refresh()
366 ddr = (void *)CFG_SYS_FSL_DDR3_ADDR; in fsl_ddr_sync_memctl_refresh()
[all …]
A Dinteractive.c610 static void print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr) in print_fsl_memctl_config_regs() argument
690 print_option_table(options, n_opts, ddr); in print_fsl_memctl_config_regs()
693 printf("debug_%02d = 0x%08X\n", i+1, ddr->debug[i]); in print_fsl_memctl_config_regs()
702 fsl_ddr_cfg_regs_t *ddr; in fsl_ddr_regs_edit() local
789 ddr = &(pinfo->fsl_ddr_config_reg[ctrl_num]); in fsl_ddr_regs_edit()
791 if (handle_option_table(options, n_opts, ddr, regname, value_str)) in fsl_ddr_regs_edit()
798 ddr->debug[i] = value; in fsl_ddr_regs_edit()
/drivers/ddr/imx/
A DKconfig1 source "drivers/ddr/imx/imx8m/Kconfig"
2 source "drivers/ddr/imx/imx8ulp/Kconfig"
3 source "drivers/ddr/imx/imx9/Kconfig"
4 source "drivers/ddr/imx/phy/Kconfig"
/drivers/
A DMakefile56 obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR) += ddr/fsl/
57 obj-$(CONFIG_ARMADA_38X) += ddr/marvell/a38x/
58 obj-$(CONFIG_ARMADA_XP) += ddr/marvell/axp/
59 obj-$(CONFIG_$(PHASE_)ALTERA_SDRAM) += ddr/altera/
60 obj-$(CONFIG_ARCH_IMX8M) += ddr/imx/imx8m/
61 obj-$(CONFIG_IMX8ULP_DRAM) += ddr/imx/imx8ulp/
62 obj-$(CONFIG_ARCH_IMX9) += ddr/imx/imx9/
81 obj-$(CONFIG_TPL_MPC8XXX_INIT_DDR) += ddr/fsl/
128 obj-$(CONFIG_MACH_PIC32) += ddr/microchip/
A DKconfig31 source "drivers/ddr/Kconfig"
35 source "drivers/ddr/fsl/Kconfig"
/drivers/ram/
A Dmpc83xx_sdram.c360 out_be32(&im->ddr.cs_config[0], 0); in mpc83xx_sdram_probe()
361 out_be32(&im->ddr.cs_config[1], 0); in mpc83xx_sdram_probe()
488 out_be32(&im->ddr.sdram_clk_cntl, clock_adjust); in mpc83xx_sdram_probe()
592 out_be32(&im->ddr.timing_cfg_0, timing_cfg_0); in mpc83xx_sdram_probe()
689 out_be32(&im->ddr.timing_cfg_1, timing_cfg_1); in mpc83xx_sdram_probe()
783 out_be32(&im->ddr.timing_cfg_2, timing_cfg_2); in mpc83xx_sdram_probe()
932 out_be32(&im->ddr.sdram_cfg, sdram_cfg); in mpc83xx_sdram_probe()
992 out_be32(&im->ddr.sdram_cfg2, sdram_cfg2); in mpc83xx_sdram_probe()
1010 out_be32(&im->ddr.sdram_mode, sdram_mode); in mpc83xx_sdram_probe()
1027 out_be32(&im->ddr.sdram_mode2, sdram_mode2); in mpc83xx_sdram_probe()
[all …]
/drivers/ddr/
A DKconfig38 source "drivers/ddr/altera/Kconfig"
39 source "drivers/ddr/imx/Kconfig"
/drivers/pinctrl/nuvoton/
A Dpinctrl-npcm7xx.c347 NPCM7XX_GRP(ddr), \
498 NPCM7XX_SFUNC(ddr);
624 NPCM7XX_MKFUNC(ddr),
824 NPCM7XX_PINCFG(110, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
825 NPCM7XX_PINCFG(111, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
826 NPCM7XX_PINCFG(112, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
827 NPCM7XX_PINCFG(113, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
925 NPCM7XX_PINCFG(208, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
926 NPCM7XX_PINCFG(209, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
927 NPCM7XX_PINCFG(210, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
[all …]
A Dpinctrl-npcm8xx.c145 FUNC(ddr, MFSEL3, 26, 110, 111, 112, 113, 208, 209, 210, 211, 212,\
/drivers/ddr/marvell/a38x/old/
A DMakefile21 CFLAGS_$(1) = -include $(srctree)/drivers/ddr/marvell/a38x/old/glue_symbol_renames.h
/drivers/ddr/altera/
A Dsequencer.h283 bool dram_is_ddr(const u8 ddr);
A Dsequencer.c59 bool dram_is_ddr(const u8 ddr) in dram_is_ddr() argument
65 if (ddr == 2 && type == 1) /* DDR2 */ in dram_is_ddr()
68 if (ddr == 3 && type == 2) /* DDR3 */ in dram_is_ddr()
/drivers/spi/
A Dca_sflash.c87 #define CA_SF_AR_DDR(ddr) (((ddr) << 28) & CA_SF_AR_DDR_MSK) argument
/drivers/mmc/
A Dmmc.c2156 #define for_each_supported_width(caps, ddr, ecbv) \ argument
2160 if ((ddr == ecbv->is_ddr) && (caps & ecbv->cap))

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