Home
last modified time | relevance | path

Searched refs:dev_read_u32_default (Results 1 – 25 of 198) sorted by relevance

12345678

/drivers/ram/
A Dmpc83xx_sdram.c407 ddr_type = dev_read_u32_default(dev, "ddr_type", 0); in mpc83xx_sdram_probe()
414 mvref_sel = dev_read_u32_default(dev, "mvref_sel", 0); in mpc83xx_sdram_probe()
421 m_odr = dev_read_u32_default(dev, "m_odr", 0); in mpc83xx_sdram_probe()
662 dev_read_u32_default(dev, "activate_to_activate", 0); in mpc83xx_sdram_probe()
796 ecc = dev_read_u32_default(dev, "ecc", 0); in mpc83xx_sdram_probe()
862 timing_2t = dev_read_u32_default(dev, "timing_2t", 0); in mpc83xx_sdram_probe()
945 dll_reset = dev_read_u32_default(dev, "dll_reset", 0); in mpc83xx_sdram_probe()
994 sdmode = dev_read_u32_default(dev, "sdmode", 0); in mpc83xx_sdram_probe()
1001 esdmode = dev_read_u32_default(dev, "esdmode", 0); in mpc83xx_sdram_probe()
1012 esdmode2 = dev_read_u32_default(dev, "esdmode2", 0); in mpc83xx_sdram_probe()
[all …]
/drivers/pinctrl/tegra/
A Dpinctrl-tegra.c26 drive_group[0].slwf = dev_read_u32_default(config, "nvidia,slew-rate-falling", PMUX_SLWF_NONE); in tegra_pinctrl_set_drive()
27 drive_group[0].slwr = dev_read_u32_default(config, "nvidia,slew-rate-rising", PMUX_SLWR_NONE); in tegra_pinctrl_set_drive()
28 drive_group[0].drvup = dev_read_u32_default(config, "nvidia,pull-up-strength", PMUX_DRVUP_NONE); in tegra_pinctrl_set_drive()
31 drive_group[0].lpmd = dev_read_u32_default(config, "nvidia,low-power-mode", PMUX_LPMD_NONE); in tegra_pinctrl_set_drive()
34 drive_group[0].schmt = dev_read_u32_default(config, "nvidia,schmitt", PMUX_SCHMT_NONE); in tegra_pinctrl_set_drive()
37 drive_group[0].hsm = dev_read_u32_default(config, "nvidia,high-speed-mode", PMUX_HSM_NONE); in tegra_pinctrl_set_drive()
177 pinmux_group[0].pull = dev_read_u32_default(config, "nvidia,pull", PMUX_PULL_NORMAL); in tegra_pinctrl_set_pin()
180 pinmux_group[0].io = dev_read_u32_default(config, "nvidia,enable-input", PMUX_PIN_NONE); in tegra_pinctrl_set_pin()
183 pinmux_group[0].lock = dev_read_u32_default(config, "nvidia,lock", PMUX_PIN_LOCK_DEFAULT); in tegra_pinctrl_set_pin()
186 pinmux_group[0].od = dev_read_u32_default(config, "nvidia,open-drain", PMUX_PIN_OD_DEFAULT); in tegra_pinctrl_set_pin()
[all …]
/drivers/mmc/
A Dnexell_dw_mmc.c153 host->buswidth = dev_read_u32_default(dev, "bus-width", 4); in nexell_dwmmc_of_to_plat()
158 val = dev_read_u32_default(dev, "index", -1); in nexell_dwmmc_of_to_plat()
165 priv->fifo_size = dev_read_u32_default(dev, "fifo-size", 0x20); in nexell_dwmmc_of_to_plat()
167 priv->frequency = dev_read_u32_default(dev, "frequency", 50000000); in nexell_dwmmc_of_to_plat()
168 priv->max_freq = dev_read_u32_default(dev, "max-frequency", 50000000); in nexell_dwmmc_of_to_plat()
170 priv->d_delay = dev_read_u32_default(dev, "drive_dly", 0); in nexell_dwmmc_of_to_plat()
171 priv->d_shift = dev_read_u32_default(dev, "drive_shift", 3); in nexell_dwmmc_of_to_plat()
172 priv->s_delay = dev_read_u32_default(dev, "sample_dly", 0); in nexell_dwmmc_of_to_plat()
173 priv->s_shift = dev_read_u32_default(dev, "sample_shift", 2); in nexell_dwmmc_of_to_plat()
174 priv->mmcboost = dev_read_u32_default(dev, "mmcboost", 0); in nexell_dwmmc_of_to_plat()
A Dnpcm_sdhci.c29 host->max_clk = dev_read_u32_default(dev, "clock-frequency", 0); in npcm_sdhci_probe()
40 vqmmc_uv = dev_read_u32_default(dev, "vqmmc-microvolt", 0); in npcm_sdhci_probe()
46 host->index = dev_read_u32_default(dev, "index", 0); in npcm_sdhci_probe()
A Dexynos_dw_mmc.c224 host->dev_index = dev_read_u32_default(dev, "index", host->dev_id); in exynos_dwmmc_of_to_plat()
248 div = dev_read_u32_default(dev, "samsung,dw-mshc-ciu-div", 0); in exynos_dwmmc_of_to_plat()
278 host->buswidth = dev_read_u32_default(dev, "bus-width", 4); in exynos_dwmmc_of_to_plat()
279 host->fifo_depth = dev_read_u32_default(dev, "fifo-depth", 0); in exynos_dwmmc_of_to_plat()
280 host->bus_hz = dev_read_u32_default(dev, "clock-frequency", 0); in exynos_dwmmc_of_to_plat()
A Dca_dw_mmc.c101 host->buswidth = dev_read_u32_default(dev, "bus-width", 1); in ca_dwmmc_of_to_plat()
102 host->bus_hz = dev_read_u32_default(dev, "max-frequency", 50000000); in ca_dwmmc_of_to_plat()
103 priv->ds = dev_read_u32_default(dev, "io_ds", 0x33); in ca_dwmmc_of_to_plat()
A Drockchip_dw_mmc.c70 host->buswidth = dev_read_u32_default(dev, "bus-width", 4); in rockchip_dwmmc_of_to_plat()
80 priv->fifo_depth = dev_read_u32_default(dev, "fifo-depth", 0); in rockchip_dwmmc_of_to_plat()
96 int val = dev_read_u32_default(dev, "max-frequency", -EINVAL); in rockchip_dwmmc_of_to_plat()
A Dadi_sdhci.c85 max_frequency = dev_read_u32_default(dev, "max-frequency", 0); in adi_dwcmshc_sdhci_probe()
121 host->bus_width = dev_read_u32_default(dev, "bus-width", 4); in adi_dwcmshc_sdhci_of_to_plat()
/drivers/cpu/
A Dmicroblaze_cpu.c56 ci->icache_size = dev_read_u32_default(dev, "i-cache-size", 0); in microblaze_set_cpuinfo_static()
57 ci->icache_line_length = dev_read_u32_default(dev, in microblaze_set_cpuinfo_static()
60 ci->dcache_size = dev_read_u32_default(dev, "d-cache-size", 0); in microblaze_set_cpuinfo_static()
61 ci->dcache_line_length = dev_read_u32_default(dev, in microblaze_set_cpuinfo_static()
64 ci->cpu_freq = dev_read_u32_default(dev, "clock-frequency", 0); in microblaze_set_cpuinfo_static()
65 ci->addr_size = dev_read_u32_default(dev, "xlnx,addr-size", 32); in microblaze_set_cpuinfo_static()
66 ci->use_mmu = dev_read_u32_default(dev, "xlnx,use-mmu", 0); in microblaze_set_cpuinfo_static()
/drivers/memory/
A Dti-aemif-cs.c119 val = dev_read_u32_default(dev, "ti,cs-write-setup-ns", U32_MAX); in aemif_cs_set_timings()
122 val = dev_read_u32_default(dev, "ti,cs-write-strobe-ns", U32_MAX); in aemif_cs_set_timings()
125 val = dev_read_u32_default(dev, "ti,cs-write-hold-ns", U32_MAX); in aemif_cs_set_timings()
128 val = dev_read_u32_default(dev, "ti,cs-read-setup-ns", U32_MAX); in aemif_cs_set_timings()
131 val = dev_read_u32_default(dev, "ti,cs-read-strobe-ns", U32_MAX); in aemif_cs_set_timings()
134 val = dev_read_u32_default(dev, "ti,cs-read-hold-ns", U32_MAX); in aemif_cs_set_timings()
137 val = dev_read_u32_default(dev, "ti,cs-min-turnaround-ns", U32_MAX); in aemif_cs_set_timings()
140 val = dev_read_u32_default(dev, "ti,cs-bus-width", 8); in aemif_cs_set_timings()
/drivers/gpio/
A Dxilinx_gpio.c272 plat->bank_max[0] = dev_read_u32_default(dev, "xlnx,gpio-width", 0); in xilinx_gpio_of_to_plat()
273 plat->bank_input[0] = dev_read_u32_default(dev, "xlnx,all-inputs", 0); in xilinx_gpio_of_to_plat()
274 plat->bank_output[0] = dev_read_u32_default(dev, "xlnx,all-outputs", 0); in xilinx_gpio_of_to_plat()
275 plat->dout_default[0] = dev_read_u32_default(dev, "xlnx,dout-default", in xilinx_gpio_of_to_plat()
278 is_dual = dev_read_u32_default(dev, "xlnx,is-dual", 0); in xilinx_gpio_of_to_plat()
280 plat->bank_max[1] = dev_read_u32_default(dev, in xilinx_gpio_of_to_plat()
282 plat->bank_input[1] = dev_read_u32_default(dev, in xilinx_gpio_of_to_plat()
284 plat->bank_output[1] = dev_read_u32_default(dev, in xilinx_gpio_of_to_plat()
286 plat->dout_default[1] = dev_read_u32_default(dev, in xilinx_gpio_of_to_plat()
A Dhsdk-creg-gpio.c86 gpio_count = dev_read_u32_default(dev, "gpio-count", 1); in hsdk_creg_gpio_probe()
87 shift = dev_read_u32_default(dev, "gpio-first-shift", 0); in hsdk_creg_gpio_probe()
88 bit_per_gpio = dev_read_u32_default(dev, "gpio-bit-per-line", 1); in hsdk_creg_gpio_probe()
89 activate = dev_read_u32_default(dev, "gpio-activate-val", 1); in hsdk_creg_gpio_probe()
90 deactivate = dev_read_u32_default(dev, "gpio-deactivate-val", 0); in hsdk_creg_gpio_probe()
/drivers/led/
A Dled_cortina.c141 dev_read_u32_default(dev, "Cortina,blink-rate1", 256); in ca_led_of_to_plat()
143 dev_read_u32_default(dev, "Cortina,blink-rate2", 512); in ca_led_of_to_plat()
149 priv->pin = dev_read_u32_default(dev, "pin", LED_MAX_COUNT); in ca_led_of_to_plat()
150 priv->blink_sel = dev_read_u32_default(dev, "blink-sel", 0); in ca_led_of_to_plat()
151 priv->off_event = dev_read_u32_default(dev, "off-event", 0); in ca_led_of_to_plat()
152 priv->blink_event = dev_read_u32_default(dev, "blink-event", 0); in ca_led_of_to_plat()
153 priv->on_event = dev_read_u32_default(dev, "on-event", 0); in ca_led_of_to_plat()
154 priv->port = dev_read_u32_default(dev, "port", 0); in ca_led_of_to_plat()
/drivers/video/tegra/
A Ddc-pwm-backlight.c115 dev_read_u32_default(dev, "nvidia,pwm-source", in tegra_pwm_backlight_probe()
118 dev_read_u32_default(dev, "nvidia,period", in tegra_pwm_backlight_probe()
121 dev_read_u32_default(dev, "nvidia,clock-div", in tegra_pwm_backlight_probe()
124 dev_read_u32_default(dev, "nvidia,clock-select", in tegra_pwm_backlight_probe()
127 dev_read_u32_default(dev, "nvidia,default-brightness", in tegra_pwm_backlight_probe()
/drivers/video/
A Dsandbox_sdl.c120 plat->xres = dev_read_u32_default(dev, "xres", LCD_MAX_WIDTH); in sandbox_sdl_bind()
121 plat->yres = dev_read_u32_default(dev, "yres", LCD_MAX_HEIGHT); in sandbox_sdl_bind()
122 l2bpp = dev_read_u32_default(dev, "log2-depth", VIDEO_BPP16); in sandbox_sdl_bind()
123 plat->rot = dev_read_u32_default(dev, "rotate", 0); in sandbox_sdl_bind()
A Daat2870_backlight.c92 priv->channels = dev_read_u32_default(dev, "channels", AAT2870_BL_CH_ALL); in aat2870_backlight_of_to_plat()
97 priv->max_current = dev_read_u32_default(dev, "current-max-microamp", in aat2870_backlight_of_to_plat()
/drivers/sysreset/
A Dpoweroff_gpio.c68 priv->active_delay_ms = dev_read_u32_default(dev, "active-delay-ms", 100); in poweroff_gpio_probe()
69 priv->inactive_delay_ms = dev_read_u32_default(dev, "inactive-delay-ms", 100); in poweroff_gpio_probe()
70 priv->timeout_ms = dev_read_u32_default(dev, "timeout-ms", 3000); in poweroff_gpio_probe()
/drivers/reset/
A Dreset-syscon.c61 priv->offset = dev_read_u32_default(dev, "offset", 0); in syscon_reset_probe()
62 priv->mask = dev_read_u32_default(dev, "mask", 0); in syscon_reset_probe()
63 priv->assert_high = dev_read_u32_default(dev, "assert-high", true); in syscon_reset_probe()
/drivers/net/
A Deth-phy-uclass.c143 uc_priv->reset_assert_delay = dev_read_u32_default(dev, "reset-assert-us", 0); in eth_phy_of_to_plat()
144 uc_priv->reset_deassert_delay = dev_read_u32_default(dev, "reset-deassert-us", 0); in eth_phy_of_to_plat()
149 dev_read_u32_default(dev, "reset-delay-us", 0); in eth_phy_of_to_plat()
151 dev_read_u32_default(dev, "reset-post-delay-us", 0); in eth_phy_of_to_plat()
/drivers/power/regulator/
A Dregulator_common.c40 plat->startup_delay_us = dev_read_u32_default(dev, in regulator_common_of_to_plat()
42 plat->off_on_delay_us = dev_read_u32_default(dev, "off-on-delay-us", 0); in regulator_common_of_to_plat()
45 dev_read_u32_default(dev, "u-boot,off-on-delay-us", 0); in regulator_common_of_to_plat()
A Dregulator-uclass.c478 uc_pdata->min_uV = dev_read_u32_default(dev, "regulator-min-microvolt", in regulator_pre_probe()
480 uc_pdata->max_uV = dev_read_u32_default(dev, "regulator-max-microvolt", in regulator_pre_probe()
482 uc_pdata->init_uV = dev_read_u32_default(dev, "regulator-init-microvolt", in regulator_pre_probe()
484 uc_pdata->min_uA = dev_read_u32_default(dev, "regulator-min-microamp", in regulator_pre_probe()
486 uc_pdata->max_uA = dev_read_u32_default(dev, "regulator-max-microamp", in regulator_pre_probe()
488 uc_pdata->ramp_delay = dev_read_u32_default(dev, "regulator-ramp-delay", in regulator_pre_probe()
/drivers/net/octeon/
A Docteon_mdio.c155 drv_ctl.s.pctl = dev_read_u32_default(dev, "cavium,pctl-drive-strength", in octeon_mdio_probe()
157 drv_ctl.s.nctl = dev_read_u32_default(dev, "cavium,nctl-drive-strength", in octeon_mdio_probe()
164 p->speed = dev_read_u32_default(dev, "cavium,max-speed", in octeon_mdio_probe()
171 sample_dly = dev_read_u32_default(dev, "cavium,sample-delay", 0); in octeon_mdio_probe()
/drivers/clk/
A Dclk_fixed_factor.c53 ff->div = dev_read_u32_default(dev, "clock-div", 1); in clk_fixed_factor_of_to_plat()
54 ff->mult = dev_read_u32_default(dev, "clock-mult", 1); in clk_fixed_factor_of_to_plat()
/drivers/timer/
A Dstarfive-timer.c53 timer_channel = dev_read_u32_default(dev, "channel", 0); in starfive_probe()
75 priv->timer_size = dev_read_u32_default(dev, "timer-size", -1U); in starfive_probe()
/drivers/watchdog/
A Datcwdt200_wdt.c180 priv->wdt_clk_src = dev_read_u32_default(dev, "clock-source", NODE_NOT_FOUND); in atcwdt_wdt_probe()
184 timer_16bit = dev_read_u32_default(dev, "16bit_timer", NODE_NOT_FOUND); in atcwdt_wdt_probe()
190 priv->clk_freq = dev_read_u32_default(dev, "clock-frequency", NODE_NOT_FOUND); in atcwdt_wdt_probe()

Completed in 61 milliseconds

12345678