| /drivers/clk/imx/ |
| A D | clk-pllv3.c | 42 u32 div_shift; member
53 u32 div = (readl(pll->base) >> pll->div_shift) & pll->div_mask; in clk_pllv3_genericv2_get_rate()
63 u32 div = (readl(pll->base) >> pll->div_shift) & pll->div_mask; in clk_pllv3_genericv2_set_rate()
77 u32 div = (readl(pll->base) >> pll->div_shift) & pll->div_mask; in clk_pllv3_generic_get_rate()
96 val &= ~(pll->div_mask << pll->div_shift); in clk_pllv3_generic_set_rate()
97 val |= (div << pll->div_shift); in clk_pllv3_generic_set_rate()
304 pll->div_shift = 0; in imx_clk_pllv3()
311 pll->div_shift = 0; in imx_clk_pllv3()
316 pll->div_shift = 0; in imx_clk_pllv3()
321 pll->div_shift = 1; in imx_clk_pllv3()
[all …]
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| /drivers/clk/airoha/ |
| A D | clk-airoha.c | 52 u8 div_shift; member
89 .div_shift = 0,
104 .div_shift = 0,
119 .div_shift = 0,
135 .div_shift = 24,
148 .div_shift = 8,
163 .div_shift = 0,
208 val >>= desc->div_shift; in airoha_clk_get_div()
367 mask = (BIT(desc->div_bits) - 1) << desc->div_shift; in airoha_clk_set_rate()
368 val = div_val << desc->div_shift; in airoha_clk_set_rate()
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| /drivers/clk/rockchip/ |
| A D | clk_rk3528.c | 1024 u32 div_mask, div_shift; in rk3528_dclk_vop_get_clk() local
1036 div_shift = DCLK_VOP_SRC0_DIV_SHIFT; in rk3528_dclk_vop_get_clk()
1044 div_shift = DCLK_VOP_SRC1_DIV_SHIFT; in rk3528_dclk_vop_get_clk()
1052 div = (con & div_mask) >> div_shift; in rk3528_dclk_vop_get_clk()
1066 u32 div_mask, div_shift; in rk3528_dclk_vop_set_clk() local
1078 div_shift = DCLK_VOP_SRC0_DIV_SHIFT; in rk3528_dclk_vop_set_clk()
1086 div_shift = DCLK_VOP_SRC1_DIV_SHIFT; in rk3528_dclk_vop_set_clk()
1119 div_shift = CLK_UART0_SRC_DIV_SHIFT; in rk3528_uart_get_rate()
1127 div_shift = CLK_UART1_SRC_DIV_SHIFT; in rk3528_uart_get_rate()
1135 div_shift = CLK_UART2_SRC_DIV_SHIFT; in rk3528_uart_get_rate()
[all …]
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| A D | clk_rk3368.c | 364 uint8_t div_shift; member
372 [0] = { .reg = 45, .div_shift = 0, .sel_shift = 7, },
373 [1] = { .reg = 45, .div_shift = 8, .sel_shift = 15, },
374 [2] = { .reg = 46, .div_shift = 8, .sel_shift = 15, },
398 div = extract_bits(val, 7, spiclk->div_shift); in rk3368_spi_get_clk()
423 ((0x7f << spiclk->div_shift) | in rk3368_spi_set_clk()
425 ((src_clk_div << spiclk->div_shift) | in rk3368_spi_set_clk()
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| A D | clk_rk3399.c | 604 u8 div_shift; member
616 .div_shift = CLK_SPI0_PLL_DIV_CON_SHIFT,
619 .div_shift = CLK_SPI1_PLL_DIV_CON_SHIFT,
622 .div_shift = CLK_SPI2_PLL_DIV_CON_SHIFT,
625 .div_shift = CLK_SPI4_PLL_DIV_CON_SHIFT,
628 .div_shift = CLK_SPI5_PLL_DIV_CON_SHIFT,
648 div = bitfield_extract(val, spiclk->div_shift, in rk3399_spi_get_clk()
673 ((CLK_SPI_PLL_DIV_CON_MASK << spiclk->div_shift) | in rk3399_spi_set_clk()
675 ((src_clk_div << spiclk->div_shift) | in rk3399_spi_set_clk()
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| A D | clk_rk3576.c | 1134 u32 mask, div_shift, sel_shift; in rk3576_dclk_vop_set_clk() local
1143 div_shift = DCLK0_VOP_SRC_DIV_SHIFT; in rk3576_dclk_vop_set_clk()
1152 div_shift = DCLK0_VOP_SRC_DIV_SHIFT; in rk3576_dclk_vop_set_clk()
1161 div_shift = DCLK0_VOP_SRC_DIV_SHIFT; in rk3576_dclk_vop_set_clk()
1176 ((div - 1) << div_shift)); in rk3576_dclk_vop_set_clk()
1184 ((div - 1) << div_shift)); in rk3576_dclk_vop_set_clk()
1230 (best_div - 1) << div_shift); in rk3576_dclk_vop_set_clk()
1277 u32 mask, div_shift, sel_shift; in rk3576_clk_csihost_set_clk() local
1283 div_shift = CLK_DSIHOST0_DIV_SHIFT; in rk3576_clk_csihost_set_clk()
1331 (best_div - 1) << div_shift); in rk3576_clk_csihost_set_clk()
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| A D | clk_rk3588.c | 1098 u32 mask, div_shift, sel_shift; in rk3588_dclk_vop_set_clk() local
1107 div_shift = DCLK0_VOP_SRC_DIV_SHIFT; in rk3588_dclk_vop_set_clk()
1116 div_shift = DCLK1_VOP_SRC_DIV_SHIFT; in rk3588_dclk_vop_set_clk()
1125 div_shift = DCLK2_VOP_SRC_DIV_SHIFT; in rk3588_dclk_vop_set_clk()
1133 div_shift = DCLK3_VOP_SRC_DIV_SHIFT; in rk3588_dclk_vop_set_clk()
1148 ((div - 1) << div_shift)); in rk3588_dclk_vop_set_clk()
1154 ((div - 1) << div_shift)); in rk3588_dclk_vop_set_clk()
1195 (best_div - 1) << div_shift); in rk3588_dclk_vop_set_clk()
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| /drivers/clk/mvebu/ |
| A D | armada-37xx-periph.c | 78 int div_shift[2]; member
116 .div_shift[0] = _s0, \
117 .div_shift[1] = _s1, \
132 .div_shift[0] = _s, \
146 .div_shift[0] = _s, \
166 .div_shift[0] = _s, \
180 .div_shift[0] = _s0, \
181 .div_shift[1] = _s1, \
281 reg = (reg >> clk->div_shift[idx]) & clk->div_mask[idx]; in get_div()
297 reg &= ~(clk->div_mask[idx] << clk->div_shift[idx]); in set_div_val()
[all …]
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| /drivers/clk/at91/ |
| A D | clk-sam9x60-pll.c | 327 if (div == ((val & pll->layout->div_mask) >> pll->layout->div_shift)) in sam9x60_div_pll_set_rate()
333 div << pll->layout->div_shift); in sam9x60_div_pll_set_rate()
363 div = (val & pll->layout->div_mask) >> pll->layout->div_shift; in sam9x60_div_pll_get_rate()
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| A D | sam9x7.c | 219 .div_shift = 0,
227 .div_shift = 0,
236 .div_shift = 12,
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| A D | pmc.h | 55 u8 div_shift; member
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| A D | sama7d65.c | 201 .div_shift = 0,
209 .div_shift = 12,
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| A D | sama7g5.c | 186 .div_shift = 0,
194 .div_shift = 12,
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| A D | sam9x60.c | 148 .div_shift = 0,
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| /drivers/clk/ |
| A D | clk_sandbox_ccf.c | 28 u32 div_shift; member
|