Searched refs:dram_timing (Results 1 – 4 of 4) sorted by relevance
| /drivers/ddr/imx/imx9/ |
| A D | ddr_init.c | 76 u32 num = dram_timing->ddrc_cfg_num; in ddrc_config()
80 ddrc_config = dram_timing->ddrc_cfg; in ddrc_config()
86 if (dram_timing->fsp_cfg) { in ddrc_config()
183 if (!dram_timing->fsp_cfg_num) { in update_umctl2_rank_space_setting()
198 if (!dram_timing->fsp_cfg_num) { in update_umctl2_rank_space_setting()
200 dram_timing->ddrc_cfg_num, in update_umctl2_rank_space_setting()
248 if (!dram_timing->fsp_cfg_num) { in update_umctl2_rank_space_setting()
250 dram_timing->ddrc_cfg_num, in update_umctl2_rank_space_setting()
364 ret = ddr_cfg_phy(dram_timing); in ddr_init()
370 update_umctl2_rank_space_setting(dram_timing, dram_timing->fsp_msg_num - 1); in ddr_init()
[all …]
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| /drivers/ddr/imx/phy/ |
| A D | ddrphy_train.c | 11 int ddr_cfg_phy(struct dram_timing_info *dram_timing) in ddr_cfg_phy() argument
21 dram_cfg = dram_timing->ddrphy_cfg; in ddr_cfg_phy()
22 num = dram_timing->ddrphy_cfg_num; in ddr_cfg_phy()
30 fsp_msg = dram_timing->fsp_msg; in ddr_cfg_phy()
31 for (i = 0; i < dram_timing->fsp_msg_num; i++) { in ddr_cfg_phy()
85 dram_cfg = dram_timing->ddrphy_pie; in ddr_cfg_phy()
86 num = dram_timing->ddrphy_pie_num; in ddr_cfg_phy()
93 ddrphy_trained_csr_save(dram_timing->ddrphy_trained_csr, in ddr_cfg_phy()
94 dram_timing->ddrphy_trained_csr_num); in ddr_cfg_phy()
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| /drivers/ddr/imx/imx8ulp/ |
| A D | ddr_init.c | 257 int ddr_init(struct dram_timing_info2 *dram_timing) in ddr_init() argument
272 save_dram_config(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE); in ddr_init()
275 for (i = 0; i < dram_timing->ctl_cfg_num; i++) in ddr_init()
276 writel(dram_timing->ctl_cfg[i].val, (ulong)dram_timing->ctl_cfg[i].reg); in ddr_init()
279 for (i = 0; i < dram_timing->pi_cfg_num; i++) in ddr_init()
280 writel(dram_timing->pi_cfg[i].val, (ulong)dram_timing->pi_cfg[i].reg); in ddr_init()
284 for (i = 0; i < dram_timing->phy_f1_cfg_num; i++) in ddr_init()
285 writel(dram_timing->phy_f1_cfg[i].val, (ulong)dram_timing->phy_f1_cfg[i].reg); in ddr_init()
289 for (i = 0; i < dram_timing->phy_f2_cfg_num; i++) in ddr_init()
290 writel(dram_timing->phy_f2_cfg[i].val, (ulong)dram_timing->phy_f2_cfg[i].reg); in ddr_init()
[all …]
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| /drivers/ddr/imx/imx8m/ |
| A D | ddr_init.c | 313 int ddr_init(struct dram_timing_info *dram_timing) in ddr_init() argument
339 initial_drate = dram_timing->fsp_msg[0].drate; in ddr_init()
348 ddr_cfg_umctl2(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num); in ddr_init()
393 ret = ddr_cfg_phy(dram_timing); in ddr_init()
413 update_umctl2_rank_space_setting(dram_timing->fsp_msg_num - 1); in ddr_init()
468 dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE); in ddr_init()
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