| /drivers/pci/ |
| A D | pcie_dw_ti.c | 62 struct pcie_dw dw; member
85 dw_pcie_dbi_write_enable(&pci->dw, true); in pcie_dw_configure()
97 dw_pcie_dbi_write_enable(&pci->dw, false); in pcie_dw_configure()
275 pci->dw.first_busno = dev_seq(dev); in pcie_dw_ti_probe()
276 pci->dw.dev = dev; in pcie_dw_ti_probe()
278 pcie_dw_setup_host(&pci->dw); in pcie_dw_ti_probe()
290 pcie_dw_get_link_speed(&pci->dw), in pcie_dw_ti_probe()
291 pcie_dw_get_link_width(&pci->dw), in pcie_dw_ti_probe()
296 pci->dw.mem.phys_start, in pcie_dw_ti_probe()
297 pci->dw.mem.bus_start, pci->dw.mem.size); in pcie_dw_ti_probe()
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| A D | pcie_dw_meson.c | 46 struct pcie_dw dw; member
112 dw_pcie_dbi_write_enable(&priv->dw, true); in meson_pcie_configure()
122 dw_pcie_dbi_write_enable(&priv->dw, false); in meson_pcie_configure()
223 dw_pcie_dbi_write_enable(&priv->dw, true); in meson_set_max_payload()
315 pcie_dw_setup_host(&priv->dw); in meson_pcie_init_port()
336 if (!priv->dw.dbi_base) in meson_pcie_parse_dt()
404 priv->dw.first_busno = dev_seq(dev); in meson_pcie_probe()
405 priv->dw.dev = dev; in meson_pcie_probe()
425 priv->dw.mem.phys_start, in meson_pcie_probe()
426 priv->dw.mem.bus_start, in meson_pcie_probe()
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| A D | pcie_dw_rockchip.c | 38 struct pcie_dw dw; member
284 dev_seq(priv->dw.dev)); in rk_pcie_link_up()
344 pcie_dw_setup_host(&priv->dw); in rockchip_pcie_init_port()
371 if (!priv->dw.dbi_base) in rockchip_pcie_parse_dt()
383 &priv->dw.cfg_size); in rockchip_pcie_parse_dt()
384 if (!priv->dw.cfg_base) in rockchip_pcie_parse_dt()
456 priv->dw.first_busno = dev_seq(dev); in rockchip_pcie_probe()
457 priv->dw.dev = dev; in rockchip_pcie_probe()
475 priv->dw.mem.phys_start, in rockchip_pcie_probe()
476 priv->dw.mem.bus_start, in rockchip_pcie_probe()
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| A D | pcie_dw_qcom.c | 36 struct pcie_dw dw; member
193 dw_pcie_dbi_write_enable(&priv->dw, true); in qcom_pcie_clear_aspm_l0s()
207 dw_pcie_dbi_write_enable(&priv->dw, true); in qcom_pcie_clear_hpc()
393 pcie_dw_setup_host(&priv->dw); in qcom_pcie_init_port()
424 if (!priv->dw.dbi_base) in qcom_pcie_parse_dt()
430 if (!priv->dw.atu_base) in qcom_pcie_parse_dt()
492 priv->dw.first_busno = dev_seq(dev); in qcom_pcie_probe()
493 priv->dw.dev = dev; in qcom_pcie_probe()
516 priv->dw.mem.phys_start, in qcom_pcie_probe()
517 priv->dw.mem.bus_start, in qcom_pcie_probe()
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| A D | pci-rcar-gen4.c | 99 struct pcie_dw dw; member
158 if (readl(rcar->dw.dbi_base + offset) & mask) in rcar_gen4_pcie_reg_test_bit()
433 rcar->dw.first_busno = dev_seq(dev); in rcar_gen4_pcie_probe()
434 rcar->dw.dev = dev; in rcar_gen4_pcie_probe()
461 pcie_dw_setup_host(&rcar->dw); in rcar_gen4_pcie_probe()
463 dw_pcie_dbi_write_enable(&rcar->dw, true); in rcar_gen4_pcie_probe()
479 pcie_dw_get_link_speed(&rcar->dw), in rcar_gen4_pcie_probe()
480 pcie_dw_get_link_width(&rcar->dw), in rcar_gen4_pcie_probe()
485 rcar->dw.mem.phys_start, in rcar_gen4_pcie_probe()
486 rcar->dw.mem.bus_start, rcar->dw.mem.size); in rcar_gen4_pcie_probe()
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| A D | pcie_dw_imx.c | 50 struct pcie_dw dw; member
73 dw_pcie_dbi_write_enable(&priv->dw, true); in pcie_dw_configure()
78 dw_pcie_dbi_write_enable(&priv->dw, false); in pcie_dw_configure()
209 priv->dw.first_busno = dev_seq(dev); in pcie_dw_imx_probe()
210 priv->dw.dev = dev; in pcie_dw_imx_probe()
211 pcie_dw_setup_host(&priv->dw); in pcie_dw_imx_probe()
220 pcie_dw_get_link_speed(&priv->dw), in pcie_dw_imx_probe()
221 pcie_dw_get_link_width(&priv->dw), in pcie_dw_imx_probe()
226 priv->dw.mem.phys_start, in pcie_dw_imx_probe()
227 priv->dw.mem.bus_start, priv->dw.mem.size); in pcie_dw_imx_probe()
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| A D | pcie_dw_sifive.c | 33 struct pcie_dw dw; member
265 val = readl(sv->dw.dbi_base + PHY_DEBUG_R1); in pcie_sifive_check_link()
394 pcie_dw_setup_host(&sv->dw); in pcie_sifive_init_port()
411 sv->dw.first_busno = dev_seq(dev); in pcie_sifive_probe()
412 sv->dw.dev = dev; in pcie_sifive_probe()
422 pcie_dw_get_link_width(&sv->dw), in pcie_sifive_probe()
428 sv->dw.mem.phys_start, in pcie_sifive_probe()
429 sv->dw.mem.bus_start, in pcie_sifive_probe()
430 sv->dw.mem.size); in pcie_sifive_probe()
448 sv->dw.dbi_base = get_fdt_addr(dev, "dbi"); in pcie_sifive_of_to_plat()
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| A D | pcie_intel_fpga.c | 149 u32 dw[4]; in tlp_read_packet() local
158 dw[count++] = cra_readl(pcie, RP_RXCPL_REG); in tlp_read_packet()
163 dw[count++] = cra_readl(pcie, RP_RXCPL_REG); in tlp_read_packet()
165 comp_status = TLP_COMP_STATUS(dw[1]); in tlp_read_packet()
172 TLP_BYTE_COUNT(dw[1]) == sizeof(u32) && in tlp_read_packet()
174 *value = dw[3]; in tlp_read_packet()
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| /drivers/power/acpi_pmc/ |
| A D | acpi-pmc-uclass.c | 41 u32 *dw; in pmc_gpe_init() local
49 dw = upriv->gpe0_dw; in pmc_gpe_init()
54 if (dw[i] & ~mask) in pmc_gpe_init()
62 if (dw[0] == dw[1] || dw[1] == dw[2]) { in pmc_gpe_init()
67 dw[i] = gpio_cfg >> gpe0_shift(upriv, i); in pmc_gpe_init()
71 gpio_cfg |= dw[i] << gpe0_shift(upriv, i); in pmc_gpe_init()
79 pinctrl_route_gpe(itss, dw[0], dw[1], dw[2]); in pmc_gpe_init()
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| /drivers/i3c/master/ |
| A D | Kconfig | 8 https://www.synopsys.com/dw/ipdir.php?ds=mipi_i3c
11 will be called dw-i3c-master.
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| A D | Makefile | 3 obj-$(CONFIG_DW_I3C_MASTER) += dw-i3c-master.o
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| /drivers/ddr/fsl/ |
| A D | main.c | 338 unsigned int dw; in __step_assign_addresses() local
341 dw = pinfo->dimm_params[i][j].primary_sdram_width; in __step_assign_addresses()
342 if ((dw == 72 || dw == 64)) { in __step_assign_addresses()
345 } else if ((dw == 40 || dw == 32)) { in __step_assign_addresses()
355 unsigned int dw; in __step_assign_addresses() local
356 dw = pinfo->dimm_params[i][j].data_width; in __step_assign_addresses()
358 && (dw == 72 || dw == 64)) { in __step_assign_addresses()
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| /drivers/timer/ |
| A D | Makefile | 17 obj-$(CONFIG_DESIGNWARE_APB_TIMER) += dw-apb-timer.o
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| /drivers/video/nexell/soc/ |
| A D | s5pxx18_soc_mlc.c | 1042 void nx_mlc_set_video_layer_scale(u32 module_index, u32 sw, u32 sh, u32 dw, in nx_mlc_set_video_layer_scale() argument
1054 if ((bhlumaenb || bhchromaenb) && dw > sw) { in nx_mlc_set_video_layer_scale()
1056 dw--; in nx_mlc_set_video_layer_scale()
1058 hscale = (sw << 11) / dw; in nx_mlc_set_video_layer_scale()
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| A D | s5pxx18_soc_mlc.h | 238 u32 dw, u32 dh, int bhlumaenb,
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| /drivers/ram/renesas/dbsc5/ |
| A D | dram.c | 2524 #define DBMEMCONF_REG(d3, row, bg, bank, col, dw) \ in dbsc5_dbsc_regset_pre() argument
2525 (((d3) << 30) | ((row) << 24) | ((bg) << 20) | ((bank) << 16) | ((col) << 8) | (dw)) in dbsc5_dbsc_regset_pre()
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