| /drivers/ddr/ |
| A D | Kconfig | 2 prompt "Method to determine DDR clock frequency"
8 The DDR clock frequency can either be defined statically now at
13 bool "Run-time DDR clock frequency"
16 bool "Build-time static DDR clock frequency"
21 int "DDR clock frequency in Hz"
25 The DDR clock frequency, specified in Hz.
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| /drivers/pwm/ |
| A D | pwm-cadence-ttc.c | 59 unsigned long frequency; member
101 period_clocks = div64_u64(((int64_t)period_ns * priv->frequency), in cadence_ttc_pwm_set_config()
124 duty_clocks = div64_u64(((int64_t)duty_ns * priv->frequency), in cadence_ttc_pwm_set_config()
195 priv->frequency = clk_get_rate(&clk); in cadence_ttc_pwm_probe()
196 if (IS_ERR_VALUE(priv->frequency)) { in cadence_ttc_pwm_probe()
198 return priv->frequency; in cadence_ttc_pwm_probe()
200 dev_dbg(dev, "Clk frequency: %ld\n", priv->frequency); in cadence_ttc_pwm_probe()
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| /drivers/mmc/ |
| A D | nexell_dw_mmc.c | 41 int frequency; member
167 priv->frequency = dev_read_u32_default(dev, "frequency", 50000000); in nexell_dwmmc_of_to_plat()
198 if (nx_dw_mmc_set_clk(host, priv->frequency * 4) != in nexell_dwmmc_probe()
199 priv->frequency * 4) { in nexell_dwmmc_probe()
201 __func__, priv->frequency * 4); in nexell_dwmmc_probe()
205 __func__, priv->frequency * 4); in nexell_dwmmc_probe()
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| /drivers/ddr/marvell/a38x/old/ |
| A D | ddr3_training_static.c | 149 enum hws_ddr_freq frequency, in ddr3_tip_write_leveling_static_config() argument
157 u32 adll_period = MEGA / freq_val[frequency] / 64; in ddr3_tip_write_leveling_static_config()
164 dev_num, if_id, frequency, adll_period)); in ddr3_tip_write_leveling_static_config()
207 enum hws_ddr_freq frequency, in ddr3_tip_read_leveling_static_config() argument
217 u32 sdr_period = MEGA / freq_val[frequency]; in ddr3_tip_read_leveling_static_config()
218 u32 ddr_period = MEGA / freq_val[frequency] / 2; in ddr3_tip_read_leveling_static_config()
219 u32 adll_period = MEGA / freq_val[frequency] / 64; in ddr3_tip_read_leveling_static_config()
230 if_id, frequency)); in ddr3_tip_read_leveling_static_config()
237 frequency) { in ddr3_tip_read_leveling_static_config()
243 cl_value = cas_latency_table[speed_bin_index].cl_val[frequency]; in ddr3_tip_read_leveling_static_config()
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| A D | ddr3_a38x.c | 589 enum hws_ddr_freq frequency) in ddr3_tip_a38x_set_divider() argument
605 divider = a38x_vco_freq_per_sar[sar_val] / freq_val[frequency]; in ddr3_tip_a38x_set_divider()
661 if ((frequency == DDR_FREQ_LOW_FREQ) || (freq_val[frequency] <= 400)) { in ddr3_tip_a38x_set_divider()
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| A D | ddr3_training.c | 96 u32 if_id, enum hws_ddr_freq frequency);
98 u32 if_id, enum hws_ddr_freq frequency);
1155 u32 if_id, enum hws_ddr_freq frequency) in adll_calibration() argument
1239 access_type, if_id, frequency)); in ddr3_tip_freq_set()
1241 if (frequency == DDR_FREQ_LOW_FREQ) in ddr3_tip_freq_set()
1275 frequency) { in ddr3_tip_freq_set()
1285 cl_val[frequency]; in ddr3_tip_freq_set()
1291 frequency, speed_bin_index)); in ddr3_tip_freq_set()
1368 frequency); in ddr3_tip_freq_set()
1379 t_hclk = MEGA / (freq_val[frequency] / 2); in ddr3_tip_freq_set()
[all …]
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| A D | ddr3_training_ip_prv_if.h | 58 enum hws_ddr_freq frequency);
68 u32 dev_num, enum hws_ddr_freq frequency,
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| /drivers/spi/ |
| A D | zynq_spi.c | 59 u32 frequency; /* input frequency */ member
153 plat->frequency = clock; in zynq_spi_probe()
154 plat->speed_hz = plat->frequency / 2; in zynq_spi_probe()
304 if (speed > plat->frequency) in zynq_spi_set_speed()
305 speed = plat->frequency; in zynq_spi_set_speed()
314 ((plat->frequency / in zynq_spi_set_speed()
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| A D | exynos_spi.c | 28 s32 frequency; /* Default clock frequency, -1 for none */ member
270 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", in exynos_spi_of_to_plat()
275 __func__, plat->regs, plat->periph_id, plat->frequency, in exynos_spi_of_to_plat()
295 priv->freq = plat->frequency; in exynos_spi_probe()
375 if (speed > plat->frequency) in exynos_spi_set_speed()
376 speed = plat->frequency; in exynos_spi_set_speed()
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| A D | tegra114_spi.c | 113 plat->frequency = dev_read_u32_default(bus, "spi-max-frequency", in tegra114_spi_of_to_plat()
118 __func__, plat->base, plat->periph_id, plat->frequency, in tegra114_spi_of_to_plat()
135 priv->freq = plat->frequency; in tegra114_spi_probe()
357 if (speed > plat->frequency) in tegra114_spi_set_speed()
358 speed = plat->frequency; in tegra114_spi_set_speed()
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| A D | tegra20_sflash.c | 106 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", in tegra20_sflash_of_to_plat()
111 __func__, plat->base, plat->periph_id, plat->frequency, in tegra20_sflash_of_to_plat()
125 priv->freq = plat->frequency; in tegra20_sflash_probe()
320 if (speed > plat->frequency) in tegra20_sflash_set_speed()
321 speed = plat->frequency; in tegra20_sflash_set_speed()
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| A D | tegra20_slink.c | 122 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", in tegra30_spi_of_to_plat()
127 __func__, plat->base, plat->periph_id, plat->frequency, in tegra30_spi_of_to_plat()
141 priv->freq = plat->frequency; in tegra30_spi_probe()
341 if (speed > plat->frequency) in tegra30_spi_set_speed()
342 speed = plat->frequency; in tegra30_spi_set_speed()
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| A D | tegra210_qspi.c | 114 plat->frequency = dev_read_u32_default(bus, "spi-max-frequency", in tegra210_qspi_of_to_plat()
120 __func__, plat->base, plat->periph_id, plat->frequency, in tegra210_qspi_of_to_plat()
135 priv->freq = plat->frequency; in tegra210_qspi_probe()
386 if (speed > plat->frequency) in tegra210_qspi_set_speed()
387 speed = plat->frequency; in tegra210_qspi_set_speed()
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| A D | uniphier_spi.c | 74 u32 frequency; /* input frequency */ member
287 if (speed > plat->frequency) in uniphier_spi_set_speed()
288 speed = plat->frequency; in uniphier_spi_set_speed()
374 plat->frequency = in uniphier_spi_of_to_plat()
380 plat->speed_hz = plat->frequency / 2; in uniphier_spi_of_to_plat()
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| A D | rk_spi.c | 46 s32 frequency; /* Default clock frequency, -1 for none */ member
184 plat->frequency = 20000000; in conv_of_plat()
209 plat->frequency = dev_read_u32_default(bus, "spi-max-frequency", in rockchip_spi_of_to_plat()
217 __func__, (uint)plat->base, plat->frequency, in rockchip_spi_of_to_plat()
267 priv->max_freq = plat->frequency; in rockchip_spi_probe()
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| A D | tegra_spi.h | 8 int frequency; /* Default clock frequency, -1 for none */ member
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| A D | mxs_spi.c | 47 s32 frequency; /* Default clock frequency, -1 for none */ member
333 priv->max_freq = plat->frequency; in mxs_spi_probe()
450 plat->frequency = in mxs_of_to_plat()
469 __func__, (uint)plat->base, plat->frequency, plat->num_cs, in mxs_of_to_plat()
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| A D | designware_spi.c | 119 s32 frequency; /* Default clock frequency, -1 for none */ member
256 plat->frequency = dev_read_u32_default(bus, "spi-max-frequency", in dw_spi_of_to_plat()
262 dev_info(bus, "max-frequency=%d\n", plat->frequency); in dw_spi_of_to_plat()
366 priv->freq = plat->frequency; in dw_spi_probe()
696 if (speed > plat->frequency) in dw_spi_set_speed()
697 speed = plat->frequency; in dw_spi_set_speed()
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| A D | zynqmp_gqspi.c | 176 u32 frequency; member
348 clk_rate = plat->frequency; in zynqmp_qspi_set_tapdelay()
403 log_debug("%s, Speed: %d, Max: %d\n", __func__, speed, plat->frequency); in zynqmp_qspi_set_speed()
413 ((plat->frequency / in zynqmp_qspi_set_speed()
420 plat->speed_hz = plat->frequency / (2 << baud_rate_val); in zynqmp_qspi_set_speed()
474 plat->frequency = clock; in zynqmp_qspi_probe()
475 plat->speed_hz = plat->frequency / 2; in zynqmp_qspi_probe()
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| /drivers/ddr/marvell/a38x/ |
| A D | ddr3_training.c | 110 u32 if_id, enum mv_ddr_freq frequency);
112 u32 if_id, enum mv_ddr_freq frequency);
1153 u32 if_id, enum mv_ddr_freq frequency) in adll_calibration() argument
1245 u32 freq = mv_ddr_freq_get(frequency); in ddr3_tip_freq_set()
1249 access_type, if_id, frequency)); in ddr3_tip_freq_set()
1251 if (frequency == MV_DDR_FREQ_LOW_FREQ) in ddr3_tip_freq_set()
1284 frequency) { in ddr3_tip_freq_set()
1309 frequency, speed_bin_index)); in ddr3_tip_freq_set()
1426 frequency); in ddr3_tip_freq_set()
1687 u32 freq = mv_ddr_freq_get(frequency); in ddr3_tip_set_timing()
[all …]
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| A D | mv_ddr_plat.c | 460 static u8 ddr3_tip_clock_mode(u32 frequency) in ddr3_tip_clock_mode() argument
462 if ((frequency == MV_DDR_FREQ_LOW_FREQ) || (mv_ddr_freq_get(frequency) <= 400)) in ddr3_tip_clock_mode()
852 enum mv_ddr_freq frequency) in ddr3_tip_a38x_set_divider() argument
858 u32 ddr_freq = mv_ddr_freq_get(frequency); in ddr3_tip_a38x_set_divider()
891 switch (frequency) { in ddr3_tip_a38x_set_divider()
965 dunit_write(0x18488, (1 << 16), ((ddr3_tip_clock_mode(frequency) & 0x1) << 16)); in ddr3_tip_a38x_set_divider()
966 dunit_write(0x1524, (1 << 15), ((ddr3_tip_clock_mode(frequency) - 1) << 15)); in ddr3_tip_a38x_set_divider()
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| A D | ddr3_training_ip_flow.h | 68 enum mv_ddr_freq frequency,
71 enum mv_ddr_freq frequency,
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| A D | ddr3_training_ip_prv_if.h | 57 enum mv_ddr_freq frequency);
67 u32 dev_num, enum mv_ddr_freq frequency,
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| /drivers/net/pfe_eth/ |
| A D | Kconfig | 22 int "Value of SPI flash max frequency for PFE firmware"
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| /drivers/led/ |
| A D | Kconfig | 201 int "blink frequency"
236 int "blink frequency"
271 int "blink frequency"
306 int "blink frequency"
341 int "blink frequency"
376 int "blink frequency"
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