1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * NVIDIA Tegra20 GPIO handling.
4 * (C) Copyright 2010-2012,2015
5 * NVIDIA Corporation <www.nvidia.com>
6 */
7
8 /*
9 * Based on (mostly copied from) kw_gpio.c based Linux 2.6 kernel driver.
10 * Tom Warren (twarren@nvidia.com)
11 */
12
13 #include <dm.h>
14 #include <log.h>
15 #include <malloc.h>
16 #include <errno.h>
17 #include <fdtdec.h>
18 #include <asm/io.h>
19 #include <asm/bitops.h>
20 #include <asm/arch/tegra.h>
21 #include <asm/gpio.h>
22 #include <dm/device-internal.h>
23 #include <dt-bindings/gpio/gpio.h>
24
25 static const int CFG_SFIO = 0;
26 static const int CFG_GPIO = 1;
27 static const int DIRECTION_INPUT = 0;
28 static const int DIRECTION_OUTPUT = 1;
29
30 struct tegra_gpio_plat {
31 struct gpio_ctlr_bank *bank;
32 const char *port_name; /* Name of port, e.g. "B" */
33 int base_gpio; /* Port number for this port (0, 1,.., n-1) */
34 };
35
36 /* Information about each port at run-time */
37 struct tegra_port_info {
38 struct gpio_ctlr_bank *bank;
39 int base_gpio; /* Port number for this port (0, 1,.., n-1) */
40 };
41
42 /* Return config of pin 'gpio' as GPIO (1) or SFIO (0) */
get_config(unsigned gpio)43 static int get_config(unsigned gpio)
44 {
45 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
46 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
47 u32 u;
48 int type;
49
50 u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);
51 type = (u >> GPIO_BIT(gpio)) & 1;
52
53 debug("get_config: port = %d, bit = %d is %s\n",
54 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");
55
56 return type ? CFG_GPIO : CFG_SFIO;
57 }
58
59 /* Config pin 'gpio' as GPIO or SFIO, based on 'type' */
set_config(unsigned gpio,int type)60 static void set_config(unsigned gpio, int type)
61 {
62 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
63 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
64 u32 u;
65
66 debug("set_config: port = %d, bit = %d, %s\n",
67 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");
68
69 u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);
70 if (type != CFG_SFIO)
71 u |= 1 << GPIO_BIT(gpio);
72 else
73 u &= ~(1 << GPIO_BIT(gpio));
74 writel(u, &bank->gpio_config[GPIO_PORT(gpio)]);
75 }
76
77 /* Return GPIO pin 'gpio' direction - 0 = input or 1 = output */
get_direction(unsigned gpio)78 static int get_direction(unsigned gpio)
79 {
80 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
81 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
82 u32 u;
83 int dir;
84
85 u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]);
86 dir = (u >> GPIO_BIT(gpio)) & 1;
87
88 debug("get_direction: port = %d, bit = %d, %s\n",
89 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), dir ? "OUT" : "IN");
90
91 return dir ? DIRECTION_OUTPUT : DIRECTION_INPUT;
92 }
93
94 /* Config GPIO pin 'gpio' as input or output (OE) as per 'output' */
set_direction(unsigned gpio,int output)95 static void set_direction(unsigned gpio, int output)
96 {
97 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
98 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
99 u32 u;
100
101 debug("set_direction: port = %d, bit = %d, %s\n",
102 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), output ? "OUT" : "IN");
103
104 u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]);
105 if (output != DIRECTION_INPUT)
106 u |= 1 << GPIO_BIT(gpio);
107 else
108 u &= ~(1 << GPIO_BIT(gpio));
109 writel(u, &bank->gpio_dir_out[GPIO_PORT(gpio)]);
110 }
111
112 /* set GPIO pin 'gpio' output bit as 0 or 1 as per 'high' */
set_level(unsigned gpio,int high)113 static void set_level(unsigned gpio, int high)
114 {
115 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
116 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
117 u32 u;
118
119 debug("set_level: port = %d, bit %d == %d\n",
120 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), high);
121
122 u = readl(&bank->gpio_out[GPIO_PORT(gpio)]);
123 if (high)
124 u |= 1 << GPIO_BIT(gpio);
125 else
126 u &= ~(1 << GPIO_BIT(gpio));
127 writel(u, &bank->gpio_out[GPIO_PORT(gpio)]);
128 }
129
130 /*
131 * Generic_GPIO primitives.
132 */
133
134 /* set GPIO pin 'gpio' as an input */
tegra_gpio_direction_input(struct udevice * dev,unsigned offset)135 static int tegra_gpio_direction_input(struct udevice *dev, unsigned offset)
136 {
137 struct tegra_port_info *state = dev_get_priv(dev);
138
139 /* Configure GPIO direction as input. */
140 set_direction(state->base_gpio + offset, DIRECTION_INPUT);
141
142 /* Enable the pin as a GPIO */
143 set_config(state->base_gpio + offset, 1);
144
145 return 0;
146 }
147
148 /* set GPIO pin 'gpio' as an output, with polarity 'value' */
tegra_gpio_direction_output(struct udevice * dev,unsigned offset,int value)149 static int tegra_gpio_direction_output(struct udevice *dev, unsigned offset,
150 int value)
151 {
152 struct tegra_port_info *state = dev_get_priv(dev);
153 int gpio = state->base_gpio + offset;
154
155 /* Configure GPIO output value. */
156 set_level(gpio, value);
157
158 /* Configure GPIO direction as output. */
159 set_direction(gpio, DIRECTION_OUTPUT);
160
161 /* Enable the pin as a GPIO */
162 set_config(state->base_gpio + offset, 1);
163
164 return 0;
165 }
166
167 /* read GPIO IN value of pin 'gpio' */
tegra_gpio_get_value(struct udevice * dev,unsigned offset)168 static int tegra_gpio_get_value(struct udevice *dev, unsigned offset)
169 {
170 struct tegra_port_info *state = dev_get_priv(dev);
171 int gpio = state->base_gpio + offset;
172 int val;
173
174 debug("%s: pin = %d (port %d:bit %d)\n", __func__,
175 gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio));
176
177 if (get_direction(gpio) == DIRECTION_INPUT)
178 val = readl(&state->bank->gpio_in[GPIO_PORT(gpio)]);
179 else
180 val = readl(&state->bank->gpio_out[GPIO_PORT(gpio)]);
181
182 return (val >> GPIO_BIT(gpio)) & 1;
183 }
184
185 /* write GPIO OUT value to pin 'gpio' */
tegra_gpio_set_value(struct udevice * dev,unsigned offset,int value)186 static int tegra_gpio_set_value(struct udevice *dev, unsigned offset, int value)
187 {
188 struct tegra_port_info *state = dev_get_priv(dev);
189 int gpio = state->base_gpio + offset;
190
191 debug("gpio_set_value: pin = %d (port %d:bit %d), value = %d\n",
192 gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio), value);
193
194 /* Configure GPIO output value. */
195 set_level(gpio, value);
196
197 return 0;
198 }
199
gpio_config_table(const struct tegra_gpio_config * config,int len)200 void gpio_config_table(const struct tegra_gpio_config *config, int len)
201 {
202 int i;
203
204 for (i = 0; i < len; i++) {
205 switch (config[i].init) {
206 case TEGRA_GPIO_INIT_IN:
207 set_direction(config[i].gpio, DIRECTION_INPUT);
208 break;
209 case TEGRA_GPIO_INIT_OUT0:
210 set_level(config[i].gpio, 0);
211 set_direction(config[i].gpio, DIRECTION_OUTPUT);
212 break;
213 case TEGRA_GPIO_INIT_OUT1:
214 set_level(config[i].gpio, 1);
215 set_direction(config[i].gpio, DIRECTION_OUTPUT);
216 break;
217 }
218 set_config(config[i].gpio, CFG_GPIO);
219 }
220 }
221
tegra_gpio_get_function(struct udevice * dev,unsigned offset)222 static int tegra_gpio_get_function(struct udevice *dev, unsigned offset)
223 {
224 struct tegra_port_info *state = dev_get_priv(dev);
225 int gpio = state->base_gpio + offset;
226
227 if (!get_config(gpio))
228 return GPIOF_FUNC;
229 else if (get_direction(gpio))
230 return GPIOF_OUTPUT;
231 else
232 return GPIOF_INPUT;
233 }
234
tegra_gpio_xlate(struct udevice * dev,struct gpio_desc * desc,struct ofnode_phandle_args * args)235 static int tegra_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
236 struct ofnode_phandle_args *args)
237 {
238 int gpio, port, ret;
239
240 gpio = args->args[0];
241 port = gpio / TEGRA_GPIOS_PER_PORT;
242 ret = device_get_child(dev, port, &desc->dev);
243 if (ret)
244 return ret;
245 desc->offset = gpio % TEGRA_GPIOS_PER_PORT;
246 desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
247
248 return 0;
249 }
250
tegra_gpio_rfree(struct udevice * dev,unsigned int offset)251 static int tegra_gpio_rfree(struct udevice *dev, unsigned int offset)
252 {
253 struct tegra_port_info *state = dev_get_priv(dev);
254
255 /* Set the pin as a SFIO */
256 set_config(state->base_gpio + offset, CFG_SFIO);
257
258 return 0;
259 }
260
261 static const struct dm_gpio_ops gpio_tegra_ops = {
262 .direction_input = tegra_gpio_direction_input,
263 .direction_output = tegra_gpio_direction_output,
264 .get_value = tegra_gpio_get_value,
265 .set_value = tegra_gpio_set_value,
266 .get_function = tegra_gpio_get_function,
267 .xlate = tegra_gpio_xlate,
268 .rfree = tegra_gpio_rfree,
269 };
270
271 /*
272 * SPL GPIO functions.
273 */
spl_gpio_output(void * regs,uint gpio,int value)274 int spl_gpio_output(void *regs, uint gpio, int value)
275 {
276 /* Configure GPIO output value. */
277 set_level(gpio, value);
278
279 /* Configure GPIO direction as output. */
280 set_direction(gpio, DIRECTION_OUTPUT);
281
282 /* Enable the pin as a GPIO */
283 set_config(gpio, 1);
284
285 return 0;
286 }
287
spl_gpio_input(void * regs,uint gpio)288 int spl_gpio_input(void *regs, uint gpio)
289 {
290 /* Configure GPIO direction as input. */
291 set_direction(gpio, DIRECTION_INPUT);
292
293 /* Enable the pin as a GPIO */
294 set_config(gpio, 1);
295
296 return 0;
297 }
298
spl_gpio_get_value(void * regs,uint gpio)299 int spl_gpio_get_value(void *regs, uint gpio)
300 {
301 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
302 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
303 int val;
304
305 if (get_direction(gpio) == DIRECTION_INPUT)
306 val = readl(&bank->gpio_in[GPIO_PORT(gpio)]);
307 else
308 val = readl(&bank->gpio_out[GPIO_PORT(gpio)]);
309
310 return (val >> GPIO_BIT(gpio)) & 1;
311 }
312
spl_gpio_set_value(void * regs,uint gpio,int value)313 int spl_gpio_set_value(void *regs, uint gpio, int value)
314 {
315 /* Configure GPIO output value. */
316 set_level(gpio, value);
317
318 return 0;
319 }
320
321 /**
322 * Returns the name of a GPIO port
323 *
324 * GPIOs are named A, B, C, ..., Z, AA, BB, CC, ...
325 *
326 * @base_port: Base port number (0, 1..n-1)
327 * Return: allocated string containing the name
328 */
gpio_port_name(int base_port)329 static char *gpio_port_name(int base_port)
330 {
331 char *name, *s;
332
333 name = malloc(3);
334 if (name) {
335 s = name;
336 *s++ = 'A' + (base_port % 26);
337 if (base_port >= 26)
338 *s++ = *name;
339 *s = '\0';
340 }
341
342 return name;
343 }
344
345 static const struct udevice_id tegra_gpio_ids[] = {
346 { .compatible = "nvidia,tegra30-gpio" },
347 { .compatible = "nvidia,tegra20-gpio" },
348 { }
349 };
350
gpio_tegra_probe(struct udevice * dev)351 static int gpio_tegra_probe(struct udevice *dev)
352 {
353 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
354 struct tegra_port_info *priv = dev_get_priv(dev);
355 struct tegra_gpio_plat *plat = dev_get_plat(dev);
356
357 /* Only child devices have ports */
358 if (!plat)
359 return 0;
360
361 priv->bank = plat->bank;
362 priv->base_gpio = plat->base_gpio;
363
364 uc_priv->gpio_count = TEGRA_GPIOS_PER_PORT;
365 uc_priv->bank_name = plat->port_name;
366
367 return 0;
368 }
369
370 /**
371 * We have a top-level GPIO device with no actual GPIOs. It has a child
372 * device for each Tegra port.
373 */
gpio_tegra_bind(struct udevice * parent)374 static int gpio_tegra_bind(struct udevice *parent)
375 {
376 struct tegra_gpio_plat *plat = dev_get_plat(parent);
377 struct gpio_ctlr *ctlr;
378 int bank_count;
379 int bank;
380 int ret;
381
382 /* If this is a child device, there is nothing to do here */
383 if (plat)
384 return 0;
385
386 /* TODO(sjg@chromium.org): Remove once SPL supports device tree */
387 #ifdef CONFIG_XPL_BUILD
388 ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
389 bank_count = TEGRA_GPIO_BANKS;
390 #else
391 {
392 int len;
393
394 /*
395 * This driver does not make use of interrupts, other than to figure
396 * out the number of GPIO banks
397 */
398 len = dev_read_size(parent, "interrupts");
399 if (len < 0)
400 return len;
401 bank_count = len / 3 / sizeof(u32);
402 ctlr = dev_read_addr_ptr(parent);
403 if (!ctlr)
404 return -EINVAL;
405 }
406 #endif
407 for (bank = 0; bank < bank_count; bank++) {
408 int port;
409
410 for (port = 0; port < TEGRA_PORTS_PER_BANK; port++) {
411 struct tegra_gpio_plat *plat;
412 struct udevice *dev;
413 int base_port;
414
415 plat = calloc(1, sizeof(*plat));
416 if (!plat)
417 return -ENOMEM;
418 plat->bank = &ctlr->gpio_bank[bank];
419 base_port = bank * TEGRA_PORTS_PER_BANK + port;
420 plat->base_gpio = TEGRA_GPIOS_PER_PORT * base_port;
421 plat->port_name = gpio_port_name(base_port);
422
423 ret = device_bind(parent, parent->driver,
424 plat->port_name, plat,
425 dev_ofnode(parent), &dev);
426 if (ret)
427 return ret;
428 }
429 }
430
431 return 0;
432 }
433
434 U_BOOT_DRIVER(gpio_tegra) = {
435 .name = "gpio_tegra",
436 .id = UCLASS_GPIO,
437 .of_match = tegra_gpio_ids,
438 .bind = gpio_tegra_bind,
439 .probe = gpio_tegra_probe,
440 .priv_auto = sizeof(struct tegra_port_info),
441 .ops = &gpio_tegra_ops,
442 };
443