Home
last modified time | relevance | path

Searched refs:grp (Results 1 – 19 of 19) sorted by relevance

/drivers/pinctrl/tegra/
A Dpinmux-common.c84 #define MUX_REG(grp) _R(0x80 + ((tegra_soc_pingroups[grp].ctl_id / 16) * 4)) argument
85 #define MUX_SHIFT(grp) ((tegra_soc_pingroups[grp].ctl_id % 16) * 2) argument
87 #define PULL_REG(grp) _R(0xa0 + ((tegra_soc_pingroups[grp].pull_id / 16) * 4)) argument
88 #define PULL_SHIFT(grp) ((tegra_soc_pingroups[grp].pull_id % 16) * 2) argument
90 #define TRI_REG(grp) _R(0x14 + (((grp) / 32) * 4)) argument
91 #define TRI_SHIFT(grp) ((grp) % 32) argument
382 u32 *reg = REG(grp); in pinmux_set_schmt()
407 u32 *reg = REG(grp); in pinmux_set_hsm()
517 u32 *reg = DRV_REG(grp); in pinmux_set_drvup_slwf()
538 u32 *reg = DRV_REG(grp); in pinmux_set_drvdn_slwr()
[all …]
A Dfuncmux-tegra20.c15 #define PINMUX(grp, mux, pupd, tri) \ argument
16 {PMUX_PINGRP_##grp, PMUX_FUNC_##mux, PMUX_PULL_##pupd, PMUX_TRI_##tri}
216 enum pmux_pingrp grp[] = {PMUX_PINGRP_KBCA, in funcmux_select() enum
222 for (i = 0; i < ARRAY_SIZE(grp); i++) { in funcmux_select()
223 pinmux_tristate_disable(grp[i]); in funcmux_select()
224 pinmux_set_func(grp[i], PMUX_FUNC_KBC); in funcmux_select()
225 pinmux_set_pullupdown(grp[i], PMUX_PULL_UP); in funcmux_select()
A Dpinctrl-tegra.c127 mipipad_group[count].grp = pad_id; in tegra_pinctrl_set_mipipad()
A Dpinmux-tegra124.c306 #define MIPIPADCTRL_GRP(grp, f0, f1) \ argument
/drivers/pinctrl/uniphier/
A Dpinctrl-uniphier.h117 #define __UNIPHIER_PINCTRL_GROUP(grp) \ argument
119 .name = #grp, \
120 .pins = grp##_pins, \
121 .num_pins = ARRAY_SIZE(grp##_pins), \
122 .muxvals = grp##_muxvals + \
123 BUILD_BUG_ON_ZERO(ARRAY_SIZE(grp##_pins) != \
124 ARRAY_SIZE(grp##_muxvals)), \
134 #define UNIPHIER_PINCTRL_GROUP(grp) \ argument
135 { .num_pins = ARRAY_SIZE(grp##_pins) + ARRAY_SIZE(grp##_muxvals) }
138 #define UNIPHIER_PINCTRL_GROUP(grp) __UNIPHIER_PINCTRL_GROUP(grp) argument
[all …]
A Dpinctrl-uniphier-core.c322 const struct uniphier_pinctrl_group *grp = in uniphier_pinconf_group_set() local
326 for (i = 0; i < grp->num_pins; i++) { in uniphier_pinconf_group_set()
327 ret = uniphier_pinconf_set(dev, grp->pins[i], param, arg); in uniphier_pinconf_group_set()
394 const struct uniphier_pinctrl_group *grp = in uniphier_pinmux_group_set() local
398 for (i = 0; i < grp->num_pins; i++) in uniphier_pinmux_group_set()
399 uniphier_pinmux_set_one(dev, grp->pins[i], grp->muxvals[i]); in uniphier_pinmux_group_set()
/drivers/pinctrl/mvebu/
A Dpinctrl-armada-37xx.c284 name, grp->name); in armada_37xx_pmx_set_by_name()
291 val = grp->val[func]; in armada_37xx_pmx_set_by_name()
299 grp->start_pin, grp->start_pin + grp->npins - 1, in armada_37xx_pmx_set_by_name()
331 if ((selector >= grp->start_pin && selector < grp->start_pin + grp->npins) || in armada_37xx_pmx_gpio_request_enable()
332 (selector >= grp->extra_pin && selector < grp->extra_pin + grp->extra_npins)) { in armada_37xx_pmx_gpio_request_enable()
377 if (selector >= grp->extra_pin && selector < grp->extra_pin + grp->extra_npins) { in armada_37xx_pmx_get_pin_muxing()
385 if (grp->val[f] == val) { in armada_37xx_pmx_get_pin_muxing()
400 if (selector >= grp->start_pin && selector < grp->start_pin + grp->npins) { in armada_37xx_pmx_get_pin_muxing()
408 if (grp->val[f] == val) { in armada_37xx_pmx_get_pin_muxing()
415 if (strncmp(grp->name, grp->funcs[f], in armada_37xx_pmx_get_pin_muxing()
[all …]
/drivers/pinctrl/mtmips/
A Dpinctrl-mtmips-common.c44 const struct mtmips_pmx_group *grp = &priv->groups[group_selector]; in mtmips_pinmux_group_set() local
48 if (!grp->nfuncs) in mtmips_pinmux_group_set()
51 for (i = 0; i < grp->nfuncs; i++) { in mtmips_pinmux_group_set()
52 if (!strcmp(grp->funcs[i].name, func->name)) { in mtmips_pinmux_group_set()
53 mtmips_pinctrl_reg_set(priv, grp->reg, grp->shift, in mtmips_pinmux_group_set()
54 grp->mask, grp->funcs[i].value); in mtmips_pinmux_group_set()
A Dpinctrl-mt7621.c193 const struct mtmips_pmx_group *grp = &mt7621_pmx_data[group_selector]; in mt7621_pinconf_group_set() local
197 if (!grp->pconf_avail) in mt7621_pinconf_group_set()
245 mtmips_pinctrl_reg_set(&priv->mp, grp->pconf_reg, grp->pconf_shift, in mt7621_pinconf_group_set()
/drivers/ddr/marvell/a38x/
A Dmv_ddr_sys_env_lib.h18 #define GPP_DATA_OUT_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x00) argument
19 #define GPP_DATA_OUT_EN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x04) argument
20 #define GPP_DATA_IN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x10) argument
/drivers/pinctrl/meson/
A Dpinctrl-meson-gx.h25 #define GROUP(grp, r, b) \ argument
27 .name = #grp, \
28 .pins = grp ## _pins, \
29 .num_pins = ARRAY_SIZE(grp ## _pins), \
A Dpinctrl-meson-axg.h43 #define GROUP(grp, f) \ argument
45 .name = #grp, \
46 .pins = grp ## _pins, \
47 .num_pins = ARRAY_SIZE(grp ## _pins), \
A Dpinctrl-meson.c298 struct meson_pmx_group *grp = &priv->data->groups[group_selector]; in meson_pinconf_group_set() local
301 for (i = 0; i < grp->num_pins; i++) { in meson_pinconf_group_set()
302 ret = meson_pinconf_set(dev, grp->pins[i], param, arg); in meson_pinconf_group_set()
/drivers/ddr/altera/
A Dsequencer.c401 scc_mgr_set(off, grp, val); in scc_mgr_set_all_ranks()
1643 rw_mgr_incr_vfifo(grp); in rw_mgr_decr_vfifo()
1653 const u32 grp) in find_vfifo_failing_read() argument
1670 rw_mgr_incr_vfifo(grp); in find_vfifo_failing_read()
1744 rw_mgr_incr_vfifo(grp); in sdr_find_phase()
1804 rw_mgr_decr_vfifo(seq, grp); in sdr_backup_phase()
1829 rw_mgr_incr_vfifo(grp); in sdr_backup_phase()
1854 rw_mgr_incr_vfifo(grp); in sdr_nonworking_phase()
1932 rw_mgr_incr_vfifo(grp); in sdr_find_window_center()
1949 const u32 grp) in rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() argument
[all …]
/drivers/pinctrl/starfive/
A Dpinctrl-jh7110-sys.c303 u32 grp; in jh7110_set_vin_group() local
309 grp = gs->group << gs->shift; in jh7110_set_vin_group()
312 grp |= readl(reg) & ~mask; in jh7110_set_vin_group()
313 writel(grp, reg); in jh7110_set_vin_group()
/drivers/net/mscc_eswitch/
A Dmscc_xfer.c65 u8 grp = 0; /* Recv everything on CPU group 0 */ in mscc_recv() local
70 BIT(grp))) in mscc_recv()
/drivers/net/phy/
A Dmicrel_ksz90x1.c81 const struct ksz90x1_reg_field *grp; member
142 val[i] = ofnode_read_u32_default(node, ofcfg->grp[i].name, ~0); in ksz90x1_of_config_group()
143 offset = ofcfg->grp[i].off; in ksz90x1_of_config_group()
146 regval |= ofcfg->grp[i].dflt << offset; in ksz90x1_of_config_group()
150 max = (1 << ofcfg->grp[i].size) - 1; in ksz90x1_of_config_group()
/drivers/pinctrl/renesas/
A Dpfc.c672 const struct sh_pfc_pin_group *grp = &priv->pfc.info->groups[group_selector]; in sh_pfc_pinctrl_group_set() local
679 for (i = 0; i < grp->nr_pins; ++i) { in sh_pfc_pinctrl_group_set()
680 idx = sh_pfc_get_pin_index(pfc, grp->pins[i]); in sh_pfc_pinctrl_group_set()
684 if (!strcmp(cfg->name, grp->name)) in sh_pfc_pinctrl_group_set()
699 for (i = 0; i < grp->nr_pins; ++i) { in sh_pfc_pinctrl_group_set()
700 ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION); in sh_pfc_pinctrl_group_set()
704 idx = sh_pfc_get_pin_index(pfc, grp->pins[i]); in sh_pfc_pinctrl_group_set()
898 const struct sh_pfc_pin_group *grp = &pfc->info->groups[group_selector]; in sh_pfc_pinconf_group_set() local
901 for (i = 0; i < grp->nr_pins; i++) in sh_pfc_pinconf_group_set()
902 sh_pfc_pinconf_set(pmx, grp->pins[i], param, arg); in sh_pfc_pinconf_group_set()
/drivers/pinctrl/mediatek/
A Dpinctrl-mtk-common.c324 const struct mtk_group_desc *grp = in mtk_pinmux_group_set() local
328 for (i = 0; i < grp->num_pins; i++) { in mtk_pinmux_group_set()
329 const int *pin_modes = grp->data; in mtk_pinmux_group_set()
331 mtk_hw_set_value(dev, grp->pins[i], PINCTRL_PIN_REG_MODE, in mtk_pinmux_group_set()
640 const struct mtk_group_desc *grp = in mtk_pinconf_group_set() local
644 for (i = 0; i < grp->num_pins; i++) { in mtk_pinconf_group_set()
645 ret = mtk_pinconf_set(dev, grp->pins[i], param, arg); in mtk_pinconf_group_set()

Completed in 56 milliseconds