| /drivers/ddr/marvell/a38x/ |
| A D | ddr3_training_pbs.c | 58 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_pbs()
88 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_pbs()
177 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_pbs()
336 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_pbs()
351 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_pbs()
374 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_pbs()
401 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_pbs()
462 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_pbs()
751 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_pbs()
858 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_pbs()
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| A D | ddr3_training_hw_algo.c | 182 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_vref()
231 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_vref()
255 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_vref()
273 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_vref()
372 [if_id]; in ddr3_tip_vref()
383 if_id, in ddr3_tip_vref()
410 [if_id]; in ddr3_tip_vref()
414 [if_id] - second_step) == lim_vref[pup][if_id]) { in ddr3_tip_vref()
487 [if_id]; in ddr3_tip_vref()
601 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_vref()
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| A D | ddr3_training_centralization.c | 85 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_centralization()
108 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_centralization()
137 for (if_id = start_if; if_id <= end_if; if_id++) { in ddr3_tip_centralization()
378 for (if_id = start_if; if_id <= end_if; if_id++) { in ddr3_tip_centralization()
494 if_id, in ddr3_tip_centralization()
500 [if_id] in ddr3_tip_centralization()
511 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_centralization()
549 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_special_rx()
577 for (if_id = start_if; if_id <= end_if; if_id++) { in ddr3_tip_special_rx()
666 if_id, in ddr3_tip_special_rx()
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| A D | ddr3_training_leveling.c | 55 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) in ddr3_tip_dynamic_read_leveling()
59 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()
118 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()
199 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()
267 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()
290 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()
303 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()
333 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_legacy_dynamic_write_leveling()
379 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_legacy_dynamic_read_leveling()
416 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_dynamic_per_bit_read_leveling()
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| A D | ddr3_debug.c | 144 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_reg_dump()
158 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_reg_dump()
412 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_print_log()
598 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_print_stability_log()
623 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_print_stability_log()
814 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_read_adll_value()
848 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_write_adll_value()
880 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in read_phase_value()
908 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in write_leveling_value()
968 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_print_adll()
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| A D | ddr3_training.c | 389 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in hws_ddr3_tip_init_controller()
673 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in hws_ddr3_tip_init_controller()
1134 for (if_id = start_if; if_id <= end_if; if_id++) { in ddr3_tip_bus_read_modify_write()
1263 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_freq_set()
1277 for (if_id = start_if; if_id <= end_if; if_id++) { in ddr3_tip_freq_set()
1891 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_write_cs_result()
1932 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_write_mrs_cmd()
1940 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_write_mrs_cmd()
2001 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_ddr3_reset_phy_regs()
2103 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_adll_regs_bypass()
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| A D | mv_ddr4_training_calibration.c | 106 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in mv_ddr4_dq_vref_calibration()
151 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in mv_ddr4_dq_vref_calibration()
187 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in mv_ddr4_dq_vref_calibration()
200 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in mv_ddr4_dq_vref_calibration()
217 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in mv_ddr4_dq_vref_calibration()
239 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in mv_ddr4_dq_vref_calibration()
271 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in mv_ddr4_dq_vref_calibration()
296 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in mv_ddr4_dq_vref_calibration()
321 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in mv_ddr4_dq_vref_calibration()
362 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in mv_ddr4_centralization()
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| A D | mv_ddr4_mpr_pda_if.c | 42 u32 if_id; in mv_ddr4_mode_regs_init() local
61 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in mv_ddr4_mode_regs_init()
62 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in mv_ddr4_mode_regs_init()
63 cl = tm->interface_params[if_id].cas_l; in mv_ddr4_mode_regs_init()
64 cwl = tm->interface_params[if_id].cas_wl; in mv_ddr4_mode_regs_init()
192 u32 val, mask, if_id = 0; in mv_ddr4_mpr_read_mode_enable() local
226 u32 val, mask, if_id = 0; in mv_ddr4_mpr_mode_disable() local
292 u32 word_idx, if_id = 0; in mv_ddr4_mpr_read() local
333 u32 if_id = 0, val = 0, mask; in mv_ddr4_mpr_write_mode_enable() local
573 u32 if_id, u32 subphy_mask, u32 cs_num) in mv_ddr4_pda_pattern_odpg_load() argument
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| A D | ddr3_training_ip_engine.c | 918 if_id); in ddr3_tip_read_training_result()
952 [if_id] + in ddr3_tip_read_training_result()
997 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_load_all_pattern_to_mem()
1002 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_load_all_pattern_to_mem()
1057 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_load_pattern_to_mem()
1243 u32 if_id, in ddr3_tip_ip_training_wrapper() argument
1302 end_if = if_id; in ddr3_tip_ip_training_wrapper()
1305 for (if_id = start_if; if_id <= end_if; if_id++) { in ddr3_tip_ip_training_wrapper()
1575 if_id, sybphy_id, byte_status[if_id][sybphy_id])); in ddr3_tip_ip_training_wrapper()
1612 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_load_phy_values()
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| A D | mv_ddr4_training.c | 43 u32 if_id; in mv_ddr4_sdram_config() local
47 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in mv_ddr4_sdram_config()
48 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in mv_ddr4_sdram_config()
295 u8 i, if_id = 0; in mv_ddr4_calibration_adjust() local
370 ncal = (read_data[if_id] & (0x3f << 10)) >> 10; in mv_ddr4_calibration_adjust()
371 pcal = (read_data[if_id] & (0x3f << 4)) >> 4; in mv_ddr4_calibration_adjust()
433 pcal = (read_data[if_id] & (0x3f << 4)) >> 4; in mv_ddr4_calibration_adjust()
449 pcal = (read_data[if_id] & (0x3F << 4)) >> 4; in mv_ddr4_calibration_adjust()
470 u32 if_id; in a39x_z1_config() local
474 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in a39x_z1_config()
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| A D | ddr3_training_ip_flow.h | 67 int ddr3_tip_write_leveling_static_config(u32 dev_num, u32 if_id,
70 int ddr3_tip_read_leveling_static_config(u32 dev_num, u32 if_id,
74 u32 if_id, u32 reg_addr, u32 data_value, u32 mask);
76 u32 if_id, u32 exp_value, u32 mask, u32 offset,
79 u32 if_id, u32 reg_addr, u32 *data, u32 mask);
82 u32 if_id, u32 phy_id,
96 int ddr3_tip_ext_read(u32 dev_num, u32 if_id, u32 reg_addr,
98 int ddr3_tip_ext_write(u32 dev_num, u32 if_id, u32 reg_addr,
101 int mv_ddr_rl_dqs_burst(u32 dev_num, u32 if_id, u32 freq);
110 u32 if_id, enum hws_pattern pattern,
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| A D | mv_ddr4_training_leveling.c | 18 static u8 mv_ddr4_xsb_comp_test(u32 dev_num, u32 subphy_num, u32 if_id, in mv_ddr4_xsb_comp_test() argument
274 u32 if_id; in mv_ddr4_dynamic_pb_wl_supp() local
339 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in mv_ddr4_dynamic_pb_wl_supp()
340 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in mv_ddr4_dynamic_pb_wl_supp()
363 ddr3_tip_bus_write(dev_num, ACCESS_TYPE_UNICAST, if_id, in mv_ddr4_dynamic_pb_wl_supp()
370 ddr3_tip_bus_write(dev_num, ACCESS_TYPE_UNICAST, if_id, in mv_ddr4_dynamic_pb_wl_supp()
378 ddr3_tip_bus_write(dev_num, ACCESS_TYPE_UNICAST, if_id, in mv_ddr4_dynamic_pb_wl_supp()
386 training_result[training_stage][if_id] = TEST_FAILED; in mv_ddr4_dynamic_pb_wl_supp()
391 if ((training_result[training_stage][if_id] == NO_TEST_DONE) || in mv_ddr4_dynamic_pb_wl_supp()
392 (training_result[training_stage][if_id] == TEST_SUCCESS)) in mv_ddr4_dynamic_pb_wl_supp()
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| A D | ddr3_training_ip_prv_if.h | 25 u8 dev_num, enum hws_access_type interface_access, u32 if_id,
28 u8 dev_num, enum hws_access_type interface_access, u32 if_id,
38 u8 dev_num, u32 if_id, enum mv_ddr_freq freq);
47 u32 dev_num, enum hws_access_type dunit_access_type, u32 if_id,
51 u32 dev_num, u32 if_id, enum hws_access_type phy_access_type,
56 u32 dev_num, enum hws_access_type access_type, u32 if_id,
68 enum hws_static_config_type static_config_type, u32 if_id);
70 u32 dev_num, u32 if_id, u32 ddr_addr, u32 num_bursts, u32 *data);
72 u32 dev_num, u32 if_id, u32 ddr_addr, u32 num_bursts, u32 *data);
81 u32 dev_num, u32 if_id, struct bist_result *pst_bist_result);
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| /drivers/ddr/marvell/a38x/old/ |
| A D | ddr3_training_pbs.c | 60 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_pbs()
92 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_pbs()
181 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_pbs()
340 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_pbs()
355 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_pbs()
378 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_pbs()
405 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_pbs()
466 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_pbs()
755 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_pbs()
858 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_pbs()
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| A D | ddr3_training_hw_algo.c | 186 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_vref()
235 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_vref()
259 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_vref()
277 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_vref()
376 [if_id]; in ddr3_tip_vref()
387 if_id, in ddr3_tip_vref()
414 [if_id]; in ddr3_tip_vref()
418 [if_id] - second_step) == lim_vref[pup][if_id]) { in ddr3_tip_vref()
491 [if_id]; in ddr3_tip_vref()
605 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_vref()
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| A D | ddr3_training_leveling.c | 97 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()
134 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()
153 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) in ddr3_tip_dynamic_read_leveling()
157 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()
216 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()
293 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()
416 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()
459 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_legacy_dynamic_write_leveling()
505 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_legacy_dynamic_read_leveling()
541 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_dynamic_per_bit_read_leveling()
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| A D | ddr3_training_centralization.c | 83 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_centralization()
106 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_centralization()
135 for (if_id = start_if; if_id <= end_if; if_id++) { in ddr3_tip_centralization()
347 for (if_id = start_if; if_id <= end_if; if_id++) { in ddr3_tip_centralization()
464 if_id, in ddr3_tip_centralization()
470 [if_id] in ddr3_tip_centralization()
481 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_centralization()
518 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_special_rx()
546 for (if_id = start_if; if_id <= end_if; if_id++) { in ddr3_tip_special_rx()
636 if_id, in ddr3_tip_special_rx()
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| A D | ddr3_training.c | 329 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in hws_ddr3_tip_init_controller()
640 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in hws_ddr3_tip_init_controller()
691 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in hws_ddr3_tip_load_topology_map()
1075 for (if_id = start_if; if_id <= end_if; if_id++) { in ddr3_tip_bus_access()
1136 for (if_id = start_if; if_id <= end_if; if_id++) { in ddr3_tip_bus_read_modify_write()
1253 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_freq_set()
1267 for (if_id = start_if; if_id <= end_if; if_id++) { in ddr3_tip_freq_set()
1752 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_get_first_active_if()
1771 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_write_cs_result()
1814 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_write_mrs_cmd()
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| A D | ddr3_debug.c | 109 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_reg_dump()
123 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_reg_dump()
367 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_print_log()
510 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_print_stability_log()
529 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_print_stability_log()
683 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in read_adll_value()
716 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in write_adll_value()
784 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_print_adll()
1263 for (if_id = start_if; if_id <= end_if; if_id++) { in ddr3_tip_sweep_test()
1393 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_run_sweep_test()
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| A D | ddr3_training_ip_engine.c | 668 if_id); in ddr3_tip_read_training_result()
687 if_id, in ddr3_tip_read_training_result()
702 [if_id] + in ddr3_tip_read_training_result()
743 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_load_all_pattern_to_mem()
748 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_load_all_pattern_to_mem()
832 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_load_pattern_to_mem()
848 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_load_pattern_to_mem()
991 u32 if_id, in ddr3_tip_ip_training_wrapper() argument
1034 end_if = if_id; in ddr3_tip_ip_training_wrapper()
1181 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_load_phy_values()
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| A D | ddr3_training_static.c | 96 u32 if_id; in ddr3_tip_static_round_trip_arr_build() local
112 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_static_round_trip_arr_build()
206 u32 if_id, in ddr3_tip_read_leveling_static_config() argument
230 if_id, frequency)); in ddr3_tip_read_leveling_static_config()
344 u32 if_id = 0; in ddr3_tip_run_static_alg() local
375 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_run_static_alg()
384 if_id, freq)); in ddr3_tip_run_static_alg()
386 (dev_num, if_id, freq, in ddr3_tip_run_static_alg()
389 (dev_num, if_id, freq, in ddr3_tip_run_static_alg()
471 u32 if_id, phy_id; in ddr3_tip_configure_phy() local
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| A D | ddr3_a38x.c | 257 u32 if_id, int enable) in ddr3_tip_a38x_pipe_enable() argument
286 u32 if_id, u32 reg_addr, u32 data_value, in ddr3_tip_a38x_if_write() argument
311 u32 if_id, u32 reg_addr, u32 *data, u32 mask) in ddr3_tip_a38x_if_read() argument
450 u32 if_id = 0; in ddr3_a38x_update_topology_map() local
454 tm->interface_params[if_id].memory_freq = freq; in ddr3_a38x_update_topology_map()
594 if (if_id != 0) { in ddr3_tip_a38x_set_divider()
597 if_id)); in ddr3_tip_a38x_set_divider()
622 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4260, in ddr3_tip_a38x_set_divider()
627 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4260, in ddr3_tip_a38x_set_divider()
632 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4268, in ddr3_tip_a38x_set_divider()
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| A D | ddr3_training_bist.c | 19 u32 if_id,
139 int ddr3_tip_bist_read_result(u32 dev_num, u32 if_id, in ddr3_tip_bist_read_result() argument
146 if (IS_ACTIVE(tm->if_act_mask, if_id) == 0) in ddr3_tip_bist_read_result()
150 if_id)); in ddr3_tip_bist_read_result()
151 ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_bist_read_result()
156 pst_bist_result->bist_fail_high = read_data[if_id]; in ddr3_tip_bist_read_result()
157 ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_bist_read_result()
162 pst_bist_result->bist_fail_low = read_data[if_id]; in ddr3_tip_bist_read_result()
169 pst_bist_result->bist_last_fail_addr = read_data[if_id]; in ddr3_tip_bist_read_result()
175 pst_bist_result->bist_error_cnt = read_data[if_id]; in ddr3_tip_bist_read_result()
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| A D | ddr3_training_ip_flow.h | 31 #define IS_ACTIVE(if_mask , if_id) \ argument
32 ((if_mask) & (1 << (if_id)))
287 int ddr3_tip_read_leveling_static_config(u32 dev_num, u32 if_id,
291 u32 if_id, u32 reg_addr, u32 data_value, u32 mask);
293 u32 if_id, u32 exp_value, u32 mask, u32 offset,
296 u32 if_id, u32 reg_addr, u32 *data, u32 mask);
299 u32 if_id, u32 phy_id,
313 int ddr3_tip_ext_read(u32 dev_num, u32 if_id, u32 reg_addr,
315 int ddr3_tip_ext_write(u32 dev_num, u32 if_id, u32 reg_addr,
326 u32 if_id, enum hws_pattern pattern,
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| A D | ddr3_training_ip_prv_if.h | 26 u8 dev_num, enum hws_access_type interface_access, u32 if_id,
29 u8 dev_num, enum hws_access_type interface_access, u32 if_id,
39 u8 dev_num, u32 if_id, enum hws_ddr_freq freq);
48 u32 dev_num, enum hws_access_type dunit_access_type, u32 if_id,
52 u32 dev_num, u32 if_id, enum hws_access_type phy_access_type,
57 u32 dev_num, enum hws_access_type access_type, u32 if_id,
69 enum hws_static_config_type static_config_type, u32 if_id);
71 u32 dev_num, u32 if_id, u32 ddr_addr, u32 num_bursts, u32 *data);
73 u32 dev_num, u32 if_id, u32 ddr_addr, u32 num_bursts, u32 *data);
82 u32 dev_num, u32 if_id, struct bist_result *pst_bist_result);
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