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Searched refs:lane_count (Results 1 – 8 of 8) sorted by relevance

/drivers/video/
A Dlogicore_dp_tx.c165 u8 lane_count; member
724 if (lane_count != LANE_COUNT_SET_1 && in is_lane_count_valid()
725 lane_count != LANE_COUNT_SET_2 && in is_lane_count_valid()
726 lane_count != LANE_COUNT_SET_4) in is_lane_count_valid()
901 dp_tx->link_config.lane_count = lane_count; in set_lane_count()
911 val |= dp_tx->link_config.lane_count; in set_lane_count()
1215 switch (lane_count) { in check_clock_recovery()
1260 switch (lane_count) { in check_channel_equalization()
1280 switch (lane_count) { in check_channel_equalization()
1625 switch (dp_tx->link_config.lane_count) { in trainig_state_adjust_lane_count()
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A Dlogicore_dp_tx_regif.h378 static inline u32 phy_status_lanes_ready_mask(u8 lane_count) in phy_status_lanes_ready_mask() argument
380 if (lane_count > 2) in phy_status_lanes_ready_mask()
383 if (lane_count == 2) in phy_status_lanes_ready_mask()
/drivers/video/tegra/tegra124/
A Ddp.c433 link_cfg->lane_count); in tegra_dc_dp_dump_link_cfg()
458 cfg->lane_count /= 2; in _tegra_dp_lower_link_config()
464 if (cfg->lane_count == 1) { in _tegra_dp_lower_link_config()
468 cfg->lane_count /= 2; in _tegra_dp_lower_link_config()
625 (12 / link_cfg->lane_count); in tegra_dc_dp_calc_config()
639 link_cfg->lane_count) - 4; in tegra_dc_dp_calc_config()
798 u32 n_lanes = cfg->lane_count; in tegra_dp_channel_eq_status()
1239 u8 lane_count; in tegra_dc_dp_fast_link_training() local
1295 link_bw, lane_count); in tegra_dc_dp_fast_link_training()
1311 u8 lane_count; in tegra_dp_do_link_training() local
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A Dsor.c215 u32 lane_count, int pu) in tegra_dc_sor_power_dplanes() argument
223 switch (lane_count) { in tegra_dc_sor_power_dplanes()
239 tegra_dc_sor_set_lane_count(dev, lane_count); in tegra_dc_sor_power_dplanes()
390 u8 *lane_count) in tegra_dc_sor_read_link_config() argument
403 *lane_count = 0; in tegra_dc_sor_read_link_config()
406 *lane_count = 1; in tegra_dc_sor_read_link_config()
409 *lane_count = 2; in tegra_dc_sor_read_link_config()
412 *lane_count = 4; in tegra_dc_sor_read_link_config()
435 switch (lane_count) { in tegra_dc_sor_set_lane_count()
896 switch (link_cfg->lane_count) { in tegra_dc_sor_power_down_unused_lanes()
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A Dsor.h854 u8 lane_count; member
884 void tegra_dc_sor_set_lane_count(struct udevice *dev, u8 lane_count);
889 u8 *lane_count);
/drivers/video/rockchip/
A Drk_edp.c351 values[1] = edp->link_train.lane_count; in rk_edp_link_configure()
392 for (lane = 0; lane < lane_count; lane++) { in rk_edp_clock_recovery()
411 for (lane = 0; lane < lane_count; lane++) { in rk_edp_channel_eq()
509 edp->link_train.lane_count); in rk_edp_link_train_cr()
522 edp->link_train.lane_count); in rk_edp_link_train_cr()
531 if (i == edp->link_train.lane_count) { in rk_edp_link_train_cr()
585 edp->link_train.lane_count); in rk_edp_link_train_ce()
597 edp->link_train.lane_count); in rk_edp_link_train_ce()
634 edp->link_train.lane_count); in rk_edp_init_training()
643 if (edp->link_train.lane_count == 0) { in rk_edp_init_training()
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/drivers/video/zynqmp/
A Dzynqmp_dpsub.c833 dp_sub->link_config.lane_count = lane_count; in set_lane_count()
835 writel(dp_sub->link_config.lane_count, in set_lane_count()
844 regval |= dp_sub->link_config.lane_count; in set_lane_count()
1071 switch (lane_count) { in check_clock_recovery()
1281 switch (lane_count) { in check_channel_equalization()
1294 switch (lane_count) { in check_channel_equalization()
1426 if ((check_clock_recovery(dev, lane_count) == 0) && in check_link_status()
1427 (check_channel_equalization(dev, lane_count) == 0) && in check_link_status()
1561 link_config->max_lane_count : dp_sub->lane_count); in dp_hpd_train()
1680 if (words_per_line % link_config->lane_count) in config_msa_recalculate()
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A Dzynqmp_dpsub.h123 u8 lane_count; member
291 u8 lane_count; member

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