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Searched refs:limit (Results 1 – 15 of 15) sorted by relevance

/drivers/rtc/
A Dds1374.c85 unsigned int limit; in rtc_get() local
94 limit = 10; in rtc_get()
109 } while ((time1 != time2) && limit--); in rtc_get()
/drivers/usb/mtu3/
A Dmtu3_core.c25 fz_bit = find_first_zero_bit(fifo->bitmap, fifo->limit); in ep_fifo_alloc()
26 if (fz_bit >= fifo->limit) in ep_fifo_alloc()
450 tx_fifo->limit = fifosize / MTU3_U3IP_EP_FIFO_UNIT; in get_ep_fifo_config()
456 rx_fifo->limit = fifosize / MTU3_U3IP_EP_FIFO_UNIT; in get_ep_fifo_config()
463 tx_fifo->limit = (fifosize / MTU3_U2IP_EP_FIFO_UNIT) >> 1; in get_ep_fifo_config()
468 tx_fifo->limit * MTU3_U2IP_EP_FIFO_UNIT; in get_ep_fifo_config()
469 rx_fifo->limit = tx_fifo->limit; in get_ep_fifo_config()
475 __func__, tx_fifo->base, tx_fifo->limit, in get_ep_fifo_config()
476 rx_fifo->base, rx_fifo->limit); in get_ep_fifo_config()
A Dmtu3.h191 u32 limit; member
/drivers/tpm/
A Dcr50_i2c.c463 size_t burstcnt, limit, sent = 0; in cr50_i2c_send() local
499 limit = min(burstcnt - 1, len); in cr50_i2c_send()
501 &buf[sent], limit) != 0) { in cr50_i2c_send()
506 sent += limit; in cr50_i2c_send()
507 len -= limit; in cr50_i2c_send()
/drivers/video/
A Dconsole_truetype.c750 int limit; in truetype_measure() local
762 limit = -1; in truetype_measure()
764 limit = tt_ceil((double)pixel_limit / met->scale); in truetype_measure()
796 if (ch == '\n' || (limit != -1 && neww >= limit)) { in truetype_measure()
A Dvidconsole-uclass.c627 const char *text, int limit, in vidconsole_measure() argument
637 ret = ops->measure(dev, name, size, text, limit, bbox, lines); in vidconsole_measure()
/drivers/mtd/ubi/
A Dbuild.c604 int limit, device_pebs; in get_bad_peb_limit() local
621 limit = mult_frac(device_pebs, max_beb_per1024, 1024); in get_bad_peb_limit()
624 if (mult_frac(limit, 1024, max_beb_per1024) < device_pebs) in get_bad_peb_limit()
625 limit += 1; in get_bad_peb_limit()
627 return limit; in get_bad_peb_limit()
/drivers/bootcount/
A DKconfig6 bool "Enable support for checking boot count limit"
8 Enable checking for exceeding the boot count limit.
184 If set to 0, do not set a boot limit in the environment.
/drivers/i3c/master/
A Ddw-i3c-master.c230 unsigned long base, limit; in dw_i3c_status_poll_timeout() local
233 limit = CONFIG_SYS_HZ * 5000 / 1000; in dw_i3c_status_poll_timeout()
240 } while (get_timer(base) < limit); in dw_i3c_status_poll_timeout()
/drivers/mtd/nand/raw/brcmnand/
A Dbrcmnand.c1034 unsigned long limit; in bcmnand_ctrl_poll_status() local
1040 limit = jiffies + msecs_to_jiffies(timeout_ms); in bcmnand_ctrl_poll_status()
1047 } while (time_after(limit, jiffies)); in bcmnand_ctrl_poll_status()
1049 unsigned long base, limit; in bcmnand_ctrl_poll_status()
1056 limit = CONFIG_SYS_HZ * timeout_ms / 1000; in bcmnand_ctrl_poll_status()
1063 } while (get_timer(base) < limit); in bcmnand_ctrl_poll_status()
/drivers/usb/gadget/
A Df_mass_storage.c1244 int len, limit; in do_mode_sense() local
1267 limit = 255; in do_mode_sense()
1271 limit = 65535; /* Should really be FSG_BUFLEN */ in do_mode_sense()
1302 if (!valid_page || len > limit) { in do_mode_sense()
/drivers/mmc/
A DKconfig117 int "Block count limit"
120 The block count limit on MMC based devices. We default to 65535 due
121 to a 16bit register limit on some hardware.
/drivers/clk/
A DKconfig21 This feature limit each identifier for each clock providers (24 bits).
/drivers/net/octeontx2/
A Dnix.c194 aura->s.limit = npa->q_len[idx]; in npa_lf_setup()
/drivers/power/
A DKconfig303 "axp pmic (a)ldo3 inrush quirk" below to enable a slew rate to limit

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