Searched refs:mul (Results 1 – 11 of 11) sorted by relevance
| /drivers/clk/ |
| A D | clk_boston.c | 32 uint32_t in_rate, mul, div; in clk_boston_get_rate() local
41 mul = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_MUL); in clk_boston_get_rate()
54 return (in_rate * mul * 1000000) / div; in clk_boston_get_rate()
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| A D | clk_zynq.c | 135 u32 clk_ctrl, reset, pwrdwn, mul, bypass; in zynq_clk_get_pll_rate() local
146 mul = 1; in zynq_clk_get_pll_rate()
148 mul = (clk_ctrl & PLLCTRL_FBDIV_MASK) >> PLLCTRL_FBDIV_SHIFT; in zynq_clk_get_pll_rate()
150 return priv->ps_clk_freq * mul; in zynq_clk_get_pll_rate()
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| A D | clk_pic32.c | 287 u32 v, idiv, mul; in pic32_get_mpll_rate() local
293 mul = (v >> MPLL_MULT_SHIFT) & MPLL_MULT; in pic32_get_mpll_rate()
297 rate = (SYS_POSC_CLK_HZ / idiv) * mul; in pic32_get_mpll_rate()
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| A D | clk_zynqmp.c | 378 u32 clk_ctrl, reset, mul; in zynqmp_clk_get_pll_rate() local
397 mul = (clk_ctrl & PLLCTRL_FBDIV_MASK) >> PLLCTRL_FBDIV_SHIFT; in zynqmp_clk_get_pll_rate()
399 freq *= mul; in zynqmp_clk_get_pll_rate()
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| /drivers/video/tegra/ |
| A D | dsi.c | 669 unsigned int hact, hsw, hbp, hfp, i, mul, div; in tegra_dsi_configure() local
719 hact = timing->hactive.typ * mul / div; in tegra_dsi_configure()
722 hsw = timing->hsync_len.typ * mul / div; in tegra_dsi_configure()
725 hbp = timing->hback_porch.typ * mul / div; in tegra_dsi_configure()
728 hfp = timing->hfront_porch.typ * mul / div; in tegra_dsi_configure()
757 value = 1 + timing->hactive.typ * mul / div; in tegra_dsi_configure()
779 delay = DIV_ROUND_UP(delay * mul, div * lanes); in tegra_dsi_configure()
783 bclk = DIV_ROUND_UP(htotal * mul, div * lanes); in tegra_dsi_configure()
788 value = 8 * mul / div; in tegra_dsi_configure()
827 unsigned int mul, div; in tegra_dsi_encoder_enable() local
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| /drivers/clk/at91/ |
| A D | clk-sam9x60-pll.c | 57 u32 *mul, u32 *frac, ulong rate, in sam9x60_frac_pll_compute_mul_frac() argument
87 *mul = nmul - 1; in sam9x60_frac_pll_compute_mul_frac()
143 u32 mul, frac, val; in sam9x60_frac_pll_get_rate() local
152 mul = (val & pll->layout->mul_mask) >> pll->layout->mul_shift; in sam9x60_frac_pll_get_rate()
154 pll_rate = (parent_rate * (mul + 1) + ((u64)parent_rate * frac >> 22)); in sam9x60_frac_pll_get_rate()
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| /drivers/clk/thead/ |
| A D | clk-th1520-ap.c | 244 unsigned long div, mul, frac; in th1520_pll_vco_recalc_rate() local
251 mul = FIELD_GET(TH1520_PLL_FBDIV, cfg0); in th1520_pll_vco_recalc_rate()
254 mul <<= TH1520_PLL_FRAC_BITS; in th1520_pll_vco_recalc_rate()
256 mul += frac; in th1520_pll_vco_recalc_rate()
260 rate = parent_rate * mul; in th1520_pll_vco_recalc_rate()
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| /drivers/clk/renesas/ |
| A D | r9a06g032-clocks.c | 130 u16 div, mul; member
173 .mul = _mul \
181 .mul = 1 \
818 rate = (unsigned long long)parent_rate * desc->mul; in r9a06g032_ffc_get_rate()
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| /drivers/clk/aspeed/ |
| A D | clk_ast2600.c | 144 uint32_t mul = 1, div = 1; in ast2600_get_pll_rate() local
197 mul = (pll_reg.b.m + 1) / (pll_reg.b.n + 1); in ast2600_get_pll_rate()
201 return ((CLKIN_25M * mul) / div); in ast2600_get_pll_rate()
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| /drivers/mtd/nand/raw/atmel/ |
| A D | nand-controller.c | 78 #define ATMEL_HSMC_NFC_CFG_DTO(cyc, mul) (((cyc) << 16) | ((mul) << 20)) argument
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| /drivers/ram/renesas/dbsc5/ |
| A D | dram.c | 2113 const u32 mul = frac ? 8 : 800000; in dbsc5_f_scale() local
2115 const u32 f_scale_div = DIV_ROUND_UP(tmp, mul * priv->ddr_mbpsdiv); in dbsc5_f_scale()
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