Home
last modified time | relevance | path

Searched refs:mux_sel (Results 1 – 5 of 5) sorted by relevance

/drivers/clk/exynos/
A Dclk-exynos7420.c32 unsigned int mux_sel[6]; member
40 unsigned int mux_sel[7]; member
132 if (readl(&topc->mux_sel[1]) & (1 << 16)) in exynos7420_clk_topc_probe()
185 if (readl(&top0->mux_sel[1]) & (1 << 16)) in exynos7420_clk_top0_probe()
/drivers/phy/ti/
A Dphy-j721e-wiz.c153 enum wiz_refclk_mux_sel mux_sel; member
173 .mux_sel = PLL0_REFCLK,
180 .mux_sel = PLL1_REFCLK,
187 .mux_sel = REFCLK_DIG,
201 .mux_sel = PLL0_REFCLK,
208 .mux_sel = PLL1_REFCLK,
215 .mux_sel = REFCLK_DIG,
494 const struct wiz_clk_mux_sel *mux_sel; in wiz_clk_set_parent() local
512 mux_sel = &wiz->clk_mux_sel[id]; in wiz_clk_set_parent()
513 num_parents = mux_sel->num_parents; in wiz_clk_set_parent()
[all …]
/drivers/phy/cadence/
A Dphy-cadence-sierra.c509 enum cdns_sierra_cmn_plllc mux_sel; member
520 .mux_sel = CMN_PLLLC,
527 .mux_sel = CMN_PLLLC1,
550 ret = regmap_field_write(sp->cmn_refrcv_refclk_plllc1en_preg[data[clk->id].mux_sel], i); in cdns_sierra_pll_mux_set_parent()
551 ret |= regmap_field_write(sp->cmn_refrcv_refclk_termen_preg[data[clk->id].mux_sel], i); in cdns_sierra_pll_mux_set_parent()
552 ret |= regmap_field_write(sp->cmn_plllc_pfdclk1_sel_preg[data[clk->id].mux_sel], in cdns_sierra_pll_mux_set_parent()
/drivers/ddr/altera/
A Dsequencer.h206 u32 mux_sel; member
A Dsequencer.c120 writel(0x3, &phy_mgr_cfg->mux_sel); in phy_mgr_initialize()
3695 writel(0x2, &phy_mgr_cfg->mux_sel); in run_mem_calibrate()

Completed in 27 milliseconds