| /drivers/clk/rockchip/ |
| A D | clk_rk3188.c | 40 u32 nr; member
108 ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1)); in rkclk_set_pll()
126 {.nf = 75, .nr = 1, .no = 6}, in rkclk_configure_ddr()
127 {.nf = 400, .nr = 9, .no = 2}, in rkclk_configure_ddr()
128 {.nf = 500, .nr = 9, .no = 2}, in rkclk_configure_ddr()
129 {.nf = 100, .nr = 3, .no = 1}, in rkclk_configure_ddr()
172 {.nf = 50, .nr = 1, .no = 2}, in rkclk_configure_cpu()
173 {.nf = 67, .nr = 1, .no = 1}, in rkclk_configure_cpu()
231 uint32_t nr, no, nf; in rkclk_pll_get_rate() local
250 nr = ((con >> CLKR_SHIFT) & CLKR_MASK) + 1; in rkclk_pll_get_rate()
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| A D | clk_rk3288.c | 40 u32 nr; member
184 {.nf = 25, .nr = 2, .no = 1}, in rkclk_configure_ddr()
185 {.nf = 400, .nr = 9, .no = 2}, in rkclk_configure_ddr()
186 {.nf = 500, .nr = 9, .no = 2}, in rkclk_configure_ddr()
187 {.nf = 100, .nr = 3, .no = 1}, in rkclk_configure_ddr()
234 uint ref_khz = OSC_HZ / 1000, nr, nf = 0; in pll_para_config() local
270 for (nr = 1; nr < max_nr && best_diff_khz; nr++) { in pll_para_config()
271 fref_khz = ref_khz / nr; in pll_para_config()
290 div->nr = nr; in pll_para_config()
545 uint32_t nr, no, nf; in rkclk_pll_get_rate() local
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| A D | clk_rk3066.c | 37 u32 nr; member
103 ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1)); in rk3066_clk_set_pll()
118 {.nf = 25, .nr = 2, .no = 1}, in rk3066_clk_configure_ddr()
119 {.nf = 400, .nr = 9, .no = 2}, in rk3066_clk_configure_ddr()
120 {.nf = 500, .nr = 9, .no = 2}, in rk3066_clk_configure_ddr()
121 {.nf = 100, .nr = 3, .no = 1}, in rk3066_clk_configure_ddr()
164 {.nf = 50, .nr = 1, .no = 2}, in rk3066_clk_configure_cpu()
165 {.nf = 59, .nr = 1, .no = 1}, in rk3066_clk_configure_cpu()
222 u32 nr, no, nf; in rk3066_clk_pll_get_rate() local
241 nr = bitfield_extract_by_mask(con, CLKR_MASK) + 1; in rk3066_clk_pll_get_rate()
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| A D | clk_rk3368.c | 34 u32 nr; member
48 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no}; \
68 uint32_t nr, no, nf; in rkclk_pll_get_rate() local
80 nr = ((con & PLL_NR_MASK) >> PLL_NR_SHIFT) + 1; in rkclk_pll_get_rate()
84 return (24 * nf / (nr * no)) * 1000000; in rkclk_pll_get_rate()
97 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; in rkclk_set_pll()
101 pll, div->nf, div->nr, div->no, vco_hz, output_hz); in rkclk_set_pll()
108 ((div->nr - 1) << PLL_NR_SHIFT) | in rkclk_set_pll()
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| /drivers/net/ |
| A D | sni_ave.c | 753 int ret, nc, nr; in ave_of_to_plat() local
785 for (nr = 0; nr < AVE_MAX_RSTS; nr++) { in ave_of_to_plat()
786 name = priv->data->reset_names[nr]; in ave_of_to_plat()
789 ret = reset_get_by_name(dev, name, &priv->rst[nr]); in ave_of_to_plat()
824 while (--nr >= 0) in ave_of_to_plat()
825 reset_free(&priv->rst[nr]); in ave_of_to_plat()
834 int ret, nc, nr; in ave_probe() local
858 for (nr = 0; nr < priv->nrsts; nr++) { in ave_probe()
859 ret = reset_deassert(&priv->rst[nr]); in ave_probe()
888 reset_release_all(priv->rst, nr); in ave_probe()
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| A D | dwc_eth_qos_rockchip.c | 46 #define GRF_BIT(nr) (BIT(nr) | BIT((nr) + 16)) argument
47 #define GRF_CLR_BIT(nr) (BIT((nr) + 16)) argument
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| /drivers/pinctrl/renesas/ |
| A D | sh_pfc.h | 715 #define PORTCR(nr, reg) { \ argument
716 PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, GROUP(-2, 2, -1, 3), \
720 0, PORT##nr##_OUT, PORT##nr##_IN, 0, \
723 PORT##nr##_FN0, PORT##nr##_FN1, \
724 PORT##nr##_FN2, PORT##nr##_FN3, \
725 PORT##nr##_FN4, PORT##nr##_FN5, \
726 PORT##nr##_FN6, PORT##nr##_FN7 \
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| /drivers/block/ |
| A D | blkmap.c | 328 lbaint_t nr, cnt; in blkmap_blk_read_slice() local
330 nr = blknr - bms->blknr; in blkmap_blk_read_slice()
332 return bms->read(bm, bms, nr, cnt, buffer); in blkmap_blk_read_slice()
361 lbaint_t nr, cnt; in blkmap_blk_write_slice() local
363 nr = blknr - bms->blknr; in blkmap_blk_write_slice()
365 return bms->write(bm, bms, nr, cnt, buffer); in blkmap_blk_write_slice()
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| /drivers/nvme/ |
| A D | nvme.h | 288 __le32 nr; member
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| /drivers/usb/cdns3/ |
| A D | gadget.h | 536 #define select_ep_in(nr) (EP_SEL_EPNO(p) | EP_SEL_DIR) argument
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