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Searched refs:offset (Results 1 – 25 of 554) sorted by relevance

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/drivers/misc/
A Dp2sb-uclass.c42 reg_addr += offset; in pcr_reg_address()
58 assert(IS_ALIGNED(offset, align)); in check_pcr_offset_align()
110 write_completion(dev, offset); in pcr_write32()
120 write_completion(dev, offset); in pcr_write16()
130 write_completion(dev, offset); in pcr_write8()
137 data32 = pcr_read32(dev, offset); in pcr_clrsetbits32()
140 pcr_write32(dev, offset, data32); in pcr_clrsetbits32()
147 data16 = pcr_read16(dev, offset); in pcr_clrsetbits16()
150 pcr_write16(dev, offset, data16); in pcr_clrsetbits16()
157 data8 = pcr_read8(dev, offset); in pcr_clrsetbits8()
[all …]
A Dsl28cpld.c10 uint offset; member
22 return dm_i2c_reg_read(mfd, offset + plat->offset); in sl28cpld_read_child()
28 return dm_i2c_reg_read(dev, offset); in sl28cpld_read()
30 return sl28cpld_read_child(dev, offset); in sl28cpld_read()
39 return dm_i2c_reg_write(mfd, offset + plat->offset, value); in sl28cpld_write_child()
45 return dm_i2c_reg_write(dev, offset, value); in sl28cpld_write()
55 val = sl28cpld_read(dev, offset); in sl28cpld_update()
62 return sl28cpld_write(dev, offset, val); in sl28cpld_update()
76 int offset; in sl28cpld_child_post_bind() local
82 if (offset == -1) in sl28cpld_child_post_bind()
[all …]
/drivers/usb/musb-new/
A Dmusb_io.h22 { return __raw_readw(addr + offset); } in musb_readw()
25 { return __raw_readl(addr + offset); } in musb_readl()
28 { __raw_writew(data, addr + offset); } in musb_writew()
31 { __raw_writel(data, addr + offset); } in musb_writel()
43 tmp = __raw_readw(addr + (offset & ~1)); in musb_readb()
44 if (offset & 1) in musb_readb()
56 tmp = __raw_readw(addr + (offset & ~1)); in musb_writeb()
57 if (offset & 1) in musb_writeb()
62 __raw_writew(tmp, addr + (offset & ~1)); in musb_writeb()
68 { return __raw_readb(addr + offset); } in musb_readb()
[all …]
/drivers/pinctrl/mscc/
A Dmscc-common.c29 if (offset < 32) in mscc_writel()
37 if (offset < 32) in mscc_readl()
45 if (offset < 32) in mscc_setbits()
53 if (offset < 32) in mscc_clrbits()
93 int f, offset, regoff; in mscc_pinmux_set_mux() local
105 offset = pin->pin; in mscc_pinmux_set_mux()
107 if (offset >= 32) { in mscc_pinmux_set_mux()
108 offset = offset % 32; in mscc_pinmux_set_mux()
184 BIT(offset % 32)) in mscc_gpio_get()
199 mscc_writel(offset, in mscc_gpio_set()
[all …]
/drivers/gpio/
A Dsandbox.c32 if (offset >= uc_priv->gpio_count) { in get_gpio_state()
37 return &state[offset]; in get_gpio_state()
118 ulong flags = *get_gpio_flags(dev, offset); in sandbox_gpio_get_flags()
139 debug("%s: offset:%u\n", __func__, offset); in sb_gpio_direction_input()
166 debug("%s: offset:%u\n", __func__, offset); in sb_gpio_get_value()
168 return sandbox_gpio_get_value(dev, offset); in sb_gpio_get_value()
180 offset); in sb_gpio_set_value()
207 desc->offset = args->args[0]; in sb_gpio_xlate()
265 gpio->pins[0] = desc->offset; in sb_gpio_get_acpi()
273 gpio->pin0_addr = 0x80012 + desc->offset; in sb_gpio_get_acpi()
[all …]
A Dintel_ich6_gpio.c71 val |= (1UL << offset); in _ich6_gpio_set_value()
73 val &= ~(1UL << offset); in _ich6_gpio_set_value()
87 val |= (1UL << offset); in _ich6_gpio_set_direction()
91 val &= ~(1UL << offset); in _ich6_gpio_set_direction()
102 int offset; in gpio_ich6_of_to_plat() local
110 if (offset == -1) { in gpio_ich6_of_to_plat()
114 plat->offset = offset; in gpio_ich6_of_to_plat()
115 plat->base_addr = gpiobase + offset; in gpio_ich6_of_to_plat()
158 if (!(tmplong & (1UL << offset))) { in ich6_gpio_request()
195 r = (tmplong & (1UL << offset)) ? 1 : 0; in ich6_gpio_get_value()
[all …]
A Dmpfs_gpio.c41 writel(old | offset, ptr); in mchp_update_gpio_reg()
43 writel(old & ~offset, ptr); in mchp_update_gpio_reg()
51 if (offset > uc_priv->gpio_count) in mchp_gpio_direction_input()
66 if (offset > uc_priv->gpio_count) in mchp_gpio_direction_output()
78 static bool mchp_gpio_get_value(struct udevice *dev, u32 offset) in mchp_gpio_get_value() argument
84 if (offset > uc_priv->gpio_count) in mchp_gpio_get_value()
90 val = (readl(plat->base + plat->regs->inp) & BIT(offset)); in mchp_gpio_get_value()
92 val = (readl(plat->base + plat->regs->outp) & BIT(offset)); in mchp_gpio_get_value()
94 return val >> offset; in mchp_gpio_get_value()
102 if (offset > uc_priv->gpio_count) in mchp_gpio_set_value()
[all …]
A Dnpcm_gpio.c28 writel(BIT(offset), priv->base + GPIO_OEC); in npcm_gpio_direction_input()
29 setbits_le32(priv->base + GPIO_IEM, BIT(offset)); in npcm_gpio_direction_input()
40 setbits_le32(priv->base + GPIO_DOUT, BIT(offset)); in npcm_gpio_direction_output()
42 clrbits_le32(priv->base + GPIO_DOUT, BIT(offset)); in npcm_gpio_direction_output()
44 clrbits_le32(priv->base + GPIO_IEM, BIT(offset)); in npcm_gpio_direction_output()
45 writel(BIT(offset), priv->base + GPIO_OES); in npcm_gpio_direction_output()
54 if (readl(priv->base + GPIO_IEM) & BIT(offset)) in npcm_gpio_get_value()
57 if (readl(priv->base + GPIO_OE) & BIT(offset)) in npcm_gpio_get_value()
69 setbits_le32(priv->base + GPIO_DOUT, BIT(offset)); in npcm_gpio_set_value()
80 if (readl(priv->base + GPIO_IEM) & BIT(offset)) in npcm_gpio_get_function()
[all …]
A Dsifive-gpio.c40 u32 bit = BIT(offset); in sifive_update_gpio_reg()
54 if (offset > uc_priv->gpio_count) in sifive_gpio_direction_input()
70 if (offset > uc_priv->gpio_count) in sifive_gpio_direction_output()
90 if (offset > uc_priv->gpio_count) in sifive_gpio_get_value()
94 dir = !(readl(plat->base + GPIO_OUTPUT_EN) & BIT(offset)); in sifive_gpio_get_value()
97 val = readl(plat->base + GPIO_INPUT_VAL) & BIT(offset); in sifive_gpio_get_value()
99 val = readl(plat->base + GPIO_OUTPUT_VAL) & BIT(offset); in sifive_gpio_get_value()
109 if (offset > uc_priv->gpio_count) in sifive_gpio_set_value()
123 if (offset > uc_priv->gpio_count) in sifive_gpio_get_function()
127 outdir = readl(plat->base + GPIO_OUTPUT_EN) & BIT(offset); in sifive_gpio_get_function()
[all …]
A Dstm32_gpio.c89 return !!(priv->gpio_range & BIT(offset)); in stm32_gpio_is_mapped()
97 if (!stm32_gpio_is_mapped(dev, offset)) in stm32_gpio_direction_input()
111 if (!stm32_gpio_is_mapped(dev, offset)) in stm32_gpio_direction_output()
116 writel(BSRR_BIT(offset, value), &regs->bsrr); in stm32_gpio_direction_output()
126 if (!stm32_gpio_is_mapped(dev, offset)) in stm32_gpio_get_value()
137 if (!stm32_gpio_is_mapped(dev, offset)) in stm32_gpio_set_value()
153 if (!stm32_gpio_is_mapped(dev, offset)) in stm32_gpio_get_function()
156 bits_index = MODE_BITS(offset); in stm32_gpio_get_function()
176 if (!stm32_gpio_is_mapped(dev, offset)) in stm32_gpio_set_flags()
208 if (!stm32_gpio_is_mapped(dev, offset)) in stm32_gpio_get_flags()
[all …]
A Dimx_rgpio2p.c44 return val & (1 << offset) ? 1 : 0; in imx_rgpio2p_is_output()
49 if ((readl(&regs->gpio_pddr) >> offset) & 0x01) in imx_rgpio2p_bank_get_direction()
64 l |= 1 << offset; in imx_rgpio2p_bank_direction()
67 l &= ~(1 << offset); in imx_rgpio2p_bank_direction()
76 writel((1 << offset), &regs->gpio_psor); in imx_rgpio2p_bank_set_value()
78 writel((1 << offset), &regs->gpio_pcor); in imx_rgpio2p_bank_set_value()
83 if (imx_rgpio2p_bank_get_direction(regs, offset) == in imx_rgpio2p_bank_get_value()
85 return (readl(&regs->gpio_pdir) >> offset) & 0x01; in imx_rgpio2p_bank_get_value()
87 return (readl(&regs->gpio_pdor) >> offset) & 0x01; in imx_rgpio2p_bank_get_value()
106 imx_rgpio2p_bank_set_value(bank->regs, offset, value); in imx_rgpio2p_direction_output()
[all …]
A Dintel_broadwell_gpio.c33 int offset; member
36 static int broadwell_gpio_request(struct udevice *dev, unsigned offset, in broadwell_gpio_request() argument
50 if (!(val & (1UL << offset))) { in broadwell_gpio_request()
64 setio_32(&regs->config[priv->offset + offset], CONFA_DIR_INPUT); in broadwell_gpio_direction_input()
74 return inl(&regs->config[priv->offset + offset]) & CONFA_LEVEL_HIGH ? in broadwell_gpio_get_value()
86 clrsetio_32(&regs->config[priv->offset + offset], CONFA_OUTPUT_HIGH, in broadwell_gpio_set_value()
98 broadwell_gpio_set_value(dev, offset, value); in broadwell_gpio_direction_output()
99 clrio_32(&regs->config[priv->offset + offset], CONFA_DIR_INPUT); in broadwell_gpio_direction_output()
108 u32 mask = 1UL << offset; in broadwell_gpio_get_function()
112 if (inl(&regs->config[priv->offset + offset]) & CONFA_DIR_INPUT) in broadwell_gpio_get_function()
[all …]
A Docteon_gpio.c64 if (offset > 63) in gpio_tx_reg()
76 if (offset > 63) in gpio_rx_dat_reg()
101 gpio_tx_reg(offset, value)); in octeon_gpio_dir_output()
114 gpio_rx_dat_reg(offset)); in octeon_gpio_get_value()
117 !!(reg & GPIO_BIT(offset))); in octeon_gpio_get_value()
119 return !!(reg & GPIO_BIT(offset)); in octeon_gpio_get_value()
123 unsigned int offset, int value) in octeon_gpio_set_value() argument
129 gpio_tx_reg(offset, value)); in octeon_gpio_set_value()
138 8 * offset); in octeon_gpio_get_function()
142 offset, val); in octeon_gpio_get_function()
[all …]
A Dmax77663_gpio.c15 #define GPIO_REG_ADDR(offset) (MAX77663_CNFG1_GPIO + (offset)) argument
35 if (offset >= NUM_GPIOS) in max77663_gpio_direction_input()
38 ret = pmic_clrsetbits(dev->parent, GPIO_REG_ADDR(offset), in max77663_gpio_direction_input()
53 if (offset >= NUM_GPIOS) in max77663_gpio_direction_output()
59 ret = pmic_clrsetbits(dev->parent, GPIO_REG_ADDR(offset), in max77663_gpio_direction_output()
66 ret = pmic_clrsetbits(dev->parent, GPIO_REG_ADDR(offset), in max77663_gpio_direction_output()
79 if (offset >= NUM_GPIOS) { in max77663_gpio_get_value()
86 return !!(ret & BIT(offset - NUM_GPIOS)); in max77663_gpio_get_value()
89 ret = pmic_reg_read(dev->parent, GPIO_REG_ADDR(offset)); in max77663_gpio_get_value()
107 if (offset >= NUM_GPIOS) in max77663_gpio_set_value()
[all …]
A Dbcm6345_gpio.c21 static int bcm6345_gpio_get_value(struct udevice *dev, unsigned offset) in bcm6345_gpio_get_value() argument
25 return !!(readl(priv->reg_data) & BIT(offset)); in bcm6345_gpio_get_value()
28 static int bcm6345_gpio_set_value(struct udevice *dev, unsigned offset, in bcm6345_gpio_set_value() argument
34 setbits_32(priv->reg_data, BIT(offset)); in bcm6345_gpio_set_value()
36 clrbits_32(priv->reg_data, BIT(offset)); in bcm6345_gpio_set_value()
45 clrbits_32(dirout, BIT(offset)); in bcm6345_gpio_set_direction()
47 setbits_32(dirout, BIT(offset)); in bcm6345_gpio_set_direction()
56 return bcm6345_gpio_set_direction(priv->reg_dirout, offset, 1); in bcm6345_gpio_direction_input()
64 bcm6345_gpio_set_value(dev, offset, value); in bcm6345_gpio_direction_output()
66 return bcm6345_gpio_set_direction(priv->reg_dirout, offset, 0); in bcm6345_gpio_direction_output()
[all …]
A Dgpio-aspeed-sgpio.c117 bank = GPIO_BANK(offset); in to_bank()
123 static bool aspeed_sgpio_is_input(unsigned int offset) in aspeed_sgpio_is_input() argument
125 return !(offset % 2); in aspeed_sgpio_is_input()
143 if (aspeed_sgpio_is_input(offset)) in aspeed_sgpio_set_value()
152 unsigned int offset) in aspeed_sgpio_direction_input() argument
154 return aspeed_sgpio_is_input(offset) ? 0 : -EINVAL; in aspeed_sgpio_direction_input()
164 ret = aspeed_sgpio_set_value(dev, offset, value); in aspeed_sgpio_set_flags()
166 ret = aspeed_sgpio_direction_input(dev, offset); in aspeed_sgpio_set_flags()
190 temp |= GPIO_BIT(offset); in aspeed_g4_reg_bit_set()
192 temp &= ~GPIO_BIT(offset); in aspeed_g4_reg_bit_set()
[all …]
A Dgpio-uniphier.c40 static void uniphier_gpio_get_bank_and_mask(unsigned int offset, in uniphier_gpio_get_bank_and_mask() argument
43 *bank = offset / UNIPHIER_GPIO_LINES_PER_BANK; in uniphier_gpio_get_bank_and_mask()
44 *mask = BIT(offset % UNIPHIER_GPIO_LINES_PER_BANK); in uniphier_gpio_get_bank_and_mask()
76 uniphier_gpio_get_bank_and_mask(offset, &bank, &mask); in uniphier_gpio_offset_write()
82 unsigned int offset, unsigned int reg) in uniphier_gpio_offset_read() argument
88 uniphier_gpio_get_bank_and_mask(offset, &bank, &mask); in uniphier_gpio_offset_read()
101 unsigned int offset) in uniphier_gpio_direction_input() argument
103 uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DIR, 1); in uniphier_gpio_direction_input()
109 unsigned int offset, int value) in uniphier_gpio_direction_output() argument
112 uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DIR, 0); in uniphier_gpio_direction_output()
[all …]
A Dgpio-rcar.c47 const u32 bit = BIT(offset); in rcar_gpio_get_value()
65 setbits_le32(priv->regs + GPIO_OUTDT, BIT(offset)); in rcar_gpio_set_value()
85 clrbits_le32(regs + GPIO_POSNEG, BIT(offset)); in rcar_gpio_set_direction()
90 clrbits_le32(regs + GPIO_INEN, BIT(offset)); in rcar_gpio_set_direction()
92 setbits_le32(regs + GPIO_INEN, BIT(offset)); in rcar_gpio_set_direction()
96 clrbits_le32(regs + GPIO_IOINTSEL, BIT(offset)); in rcar_gpio_set_direction()
100 setbits_le32(regs + GPIO_INOUTSEL, BIT(offset)); in rcar_gpio_set_direction()
102 clrbits_le32(regs + GPIO_INOUTSEL, BIT(offset)); in rcar_gpio_set_direction()
107 rcar_gpio_set_direction(dev, offset, false); in rcar_gpio_direction_input()
116 rcar_gpio_set_value(dev, offset, value); in rcar_gpio_direction_output()
[all …]
A Dgpio-adi-adsp.c58 u32 port, offset; in adsp_gpio_input() local
63 offset = get_offset(pin); in adsp_gpio_input()
68 iowrite16(BIT(offset), portbase + ADSP_PORT_REG_INEN_SET); in adsp_gpio_input()
78 u32 port, offset; in adsp_gpio_output() local
83 offset = get_offset(pin); in adsp_gpio_output()
93 iowrite16(BIT(offset), portbase + ADSP_PORT_REG_DIR_SET); in adsp_gpio_output()
104 u32 port, offset; in adsp_gpio_get_value() local
110 offset = get_offset(pin); in adsp_gpio_get_value()
114 return !!(val & BIT(offset)); in adsp_gpio_get_value()
123 u32 port, offset; in adsp_gpio_set_value() local
[all …]
/drivers/pinctrl/
A Dpinctrl-stmfx.c62 #define get_reg(offset) ((offset) / NR_GPIOS_PER_REG) argument
63 #define get_shift(offset) ((offset) % NR_GPIOS_PER_REG) argument
64 #define get_mask(offset) (BIT(get_shift(offset))) argument
82 u8 reg = reg_base + get_reg(offset); in stmfx_read_reg()
83 u32 mask = get_mask(offset); in stmfx_read_reg()
96 u8 reg = reg_base + get_reg(offset); in stmfx_write_reg()
97 u32 mask = get_mask(offset); in stmfx_write_reg()
138 u32 mask = get_mask(offset); in stmfx_gpio_set()
214 ret = stmfx_conf_get_type(dev, offset); in stmfx_gpio_get_flags()
220 ret = stmfx_gpio_get(dev, offset); in stmfx_gpio_get_flags()
[all …]
/drivers/pinctrl/rockchip/
A Dpinctrl-rockchip.h210 int offset; member
260 int offset; member
294 { .offset = -1 }, \
295 { .offset = -1 }, \
296 { .offset = -1 }, \
297 { .offset = -1 }, \
335 { .offset = -1 }, \
336 { .offset = -1 }, \
337 { .offset = -1 }, \
338 { .offset = -1 }, \
[all …]
/drivers/bios_emulator/x86emu/
A Ddecode.c304 uint offset) in fetch_data_byte() argument
323 uint offset) in fetch_data_word() argument
342 uint offset) in fetch_data_long() argument
363 uint offset) in fetch_data_byte_abs() argument
384 uint offset) in fetch_data_word_abs() argument
405 uint offset) in fetch_data_long_abs() argument
426 uint offset, in store_data_byte() argument
448 uint offset, in store_data_word() argument
470 uint offset, in store_data_long() argument
493 uint offset, in store_data_byte_abs() argument
[all …]
/drivers/pci/
A Dpci_octeontx.c100 uint offset, ulong *valuep, in octeontx_ecam_read_config() argument
118 uint offset, ulong value, in octeontx_ecam_write_config() argument
136 uint offset, ulong *valuep, in octeontx_pem_read_config() argument
157 offset >= PCI_PRIMARY_BUS && in octeontx_pem_read_config()
158 offset <= PCI_SUBORDINATE_BUS && in octeontx_pem_read_config()
166 uint offset, ulong value, in octeontx_pem_write_config() argument
181 offset >= PCI_PRIMARY_BUS && in octeontx_pem_write_config()
199 uint offset, ulong *valuep, in octeontx2_pem_read_config() argument
223 uint offset, ulong value, in octeontx2_pem_write_config() argument
245 uint offset, ulong *valuep, in pci_octeontx_read_config() argument
[all …]
A Dpcie_intel_fpga.c95 pci_dev_t bdf, int offset) in intel_fpga_pcie_hide_rc_bar() argument
248 uint offset, ulong value, in intel_fpga_pcie_rp_wr_conf() argument
260 if (offset == PCI_PRIMARY_BUS) in intel_fpga_pcie_rp_wr_conf()
271 return 1 << (offset & 3); in pcie_get_byte_en()
273 return 3 << (offset & 3); in pcie_get_byte_en()
280 pci_dev_t bdf, uint offset, in _pcie_intel_fpga_read_config() argument
290 offset, valuep, size); in _pcie_intel_fpga_read_config()
299 offset, size, data); in _pcie_intel_fpga_read_config()
306 pci_dev_t bdf, uint offset, in _pcie_intel_fpga_write_config() argument
315 offset, size, value); in _pcie_intel_fpga_write_config()
[all …]
/drivers/clk/starfive/
A Dclk-jh7110-pll.c184 .offset = &jh7110_pll0_offset,
191 .offset = &jh7110_pll1_offset,
226 PLLX_SET(pll->offset->pd, pll->offset->pd_mask, PLL_PD_OFF); in jh7110_pll_set_rate()
227 PLLX_SET(pll->offset->dacpd, pll->offset->dacpd_mask, 1); in jh7110_pll_set_rate()
228 PLLX_SET(pll->offset->dsmpd, pll->offset->dsmpd_mask, 1); in jh7110_pll_set_rate()
229 PLLX_SET(pll->offset->prediv, pll->offset->prediv_mask, rate->prediv); in jh7110_pll_set_rate()
230 PLLX_SET(pll->offset->fbdiv, pll->offset->fbdiv_mask, rate->fbdiv); in jh7110_pll_set_rate()
231 PLLX_SET(pll->offset->postdiv1, pll->offset->postdiv1_mask, 0); in jh7110_pll_set_rate()
232 PLLX_SET(pll->offset->pd, pll->offset->pd_mask, PLL_PD_ON); in jh7110_pll_set_rate()
262 pll->offset->frac_mask); in jh7110_pllx_recalc_rate()
[all …]

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