1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2008 by NXP Semiconductors
4 * @Author: Based on code by Kevin Wells
5 * @Descr: USB driver - Embedded Artists LPC3250 OEM Board support functions
6 *
7 * Copyright (c) 2015 Tyco Fire Protection Products.
8 */
9
10 #include <dm.h>
11 #include <errno.h>
12 #include <init.h>
13 #include <log.h>
14 #include <wait_bit.h>
15 #include <asm/io.h>
16 #include <asm/arch/cpu.h>
17 #include <asm/arch/clk.h>
18 #include <asm/arch/i2c.h>
19 #include <usb.h>
20 #include <i2c.h>
21
22 /* OTG I2C controller module register structures */
23 struct otgi2c_regs {
24 u32 otg_i2c_txrx; /* OTG I2C Tx/Rx Data FIFO */
25 u32 otg_i2c_stat; /* OTG I2C Status Register */
26 u32 otg_i2c_ctrl; /* OTG I2C Control Register */
27 u32 otg_i2c_clk_hi; /* OTG I2C Clock Divider high */
28 u32 otg_i2c_clk_lo; /* OTG I2C Clock Divider low */
29 };
30
31 /* OTG controller module register structures */
32 struct otg_regs {
33 u32 reserved1[64];
34 u32 otg_int_sts; /* OTG int status register */
35 u32 otg_int_enab; /* OTG int enable register */
36 u32 otg_int_set; /* OTG int set register */
37 u32 otg_int_clr; /* OTG int clear register */
38 u32 otg_sts_ctrl; /* OTG status/control register */
39 u32 otg_timer; /* OTG timer register */
40 u32 reserved2[122];
41 struct otgi2c_regs otg_i2c;
42 u32 reserved3[824];
43 u32 otg_clk_ctrl; /* OTG clock control reg */
44 u32 otg_clk_sts; /* OTG clock status reg */
45 };
46
47 /* otg_sts_ctrl register definitions */
48 #define OTG_HOST_EN (1 << 0) /* Enable host mode */
49
50 /* otg_clk_ctrl and otg_clk_sts register definitions */
51 #define OTG_CLK_AHB_EN (1 << 4) /* Enable AHB clock */
52 #define OTG_CLK_OTG_EN (1 << 3) /* Enable OTG clock */
53 #define OTG_CLK_I2C_EN (1 << 2) /* Enable I2C clock */
54 #define OTG_CLK_HOST_EN (1 << 0) /* Enable host clock */
55
56 /* ISP1301 USB transceiver I2C registers */
57 #define MC1_SPEED_REG (1 << 0)
58 #define MC1_DAT_SE0 (1 << 2)
59 #define MC1_UART_EN (1 << 6)
60
61 #define MC2_SPD_SUSP_CTRL (1 << 1)
62 #define MC2_BI_DI (1 << 2)
63 #define MC2_PSW_EN (1 << 6)
64
65 #define OTG1_DP_PULLUP (1 << 0)
66 #define OTG1_DM_PULLUP (1 << 1)
67 #define OTG1_DP_PULLDOWN (1 << 2)
68 #define OTG1_DM_PULLDOWN (1 << 3)
69 #define OTG1_VBUS_DRV (1 << 5)
70
71 #define ISP1301_I2C_ADDR CFG_USB_ISP1301_I2C_ADDR
72
73 #define ISP1301_I2C_MODE_CONTROL_1_SET 0x04
74 #define ISP1301_I2C_MODE_CONTROL_1_CLR 0x05
75 #define ISP1301_I2C_MODE_CONTROL_2_SET 0x12
76 #define ISP1301_I2C_MODE_CONTROL_2_CLR 0x13
77 #define ISP1301_I2C_OTG_CONTROL_1_SET 0x06
78 #define ISP1301_I2C_OTG_CONTROL_1_CLR 0x07
79 #define ISP1301_I2C_INTERRUPT_LATCH_CLR 0x0B
80 #define ISP1301_I2C_INTERRUPT_FALLING_CLR 0x0D
81 #define ISP1301_I2C_INTERRUPT_RISING_CLR 0x0F
82
83 static struct otg_regs *otg = (struct otg_regs *)USB_BASE;
84 static struct clk_pm_regs *clk_pwr = (struct clk_pm_regs *)CLK_PM_BASE;
85
isp1301_set_value(struct udevice * dev,int reg,u8 value)86 static int isp1301_set_value(struct udevice *dev, int reg, u8 value)
87 {
88 #if !CONFIG_IS_ENABLED(DM_I2C)
89 return i2c_write(ISP1301_I2C_ADDR, reg, 1, &value, 1);
90 #else
91 return dm_i2c_write(dev, reg, &value, 1);
92 #endif
93 }
94
isp1301_configure(struct udevice * dev)95 static void isp1301_configure(struct udevice *dev)
96 {
97 /*
98 * LPC32XX only supports DAT_SE0 USB mode
99 * This sequence is important
100 */
101
102 /* Disable transparent UART mode first */
103 isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_1_CLR, MC1_UART_EN);
104
105 isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_1_CLR, ~MC1_SPEED_REG);
106 isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_1_SET, MC1_SPEED_REG);
107 isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_2_CLR, ~0);
108 isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_2_SET,
109 MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL);
110
111 isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_CLR, ~0);
112 isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_1_SET, MC1_DAT_SE0);
113 isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_SET,
114 OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN);
115 isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_CLR,
116 OTG1_DM_PULLUP | OTG1_DP_PULLUP);
117 isp1301_set_value(dev, ISP1301_I2C_INTERRUPT_LATCH_CLR, ~0);
118 isp1301_set_value(dev, ISP1301_I2C_INTERRUPT_FALLING_CLR, ~0);
119 isp1301_set_value(dev, ISP1301_I2C_INTERRUPT_RISING_CLR, ~0);
120
121 /* Enable usb_need_clk clock after transceiver is initialized */
122 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_USBDVND_EN);
123 }
124
usbpll_setup(void)125 static int usbpll_setup(void)
126 {
127 u32 ret;
128
129 /* make sure clocks are disabled */
130 clrbits_le32(&clk_pwr->usb_ctrl,
131 CLK_USBCTRL_CLK_EN1 | CLK_USBCTRL_CLK_EN2);
132
133 /* start PLL clock input */
134 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_CLK_EN1);
135
136 /* Setup PLL. */
137 setbits_le32(&clk_pwr->usb_ctrl,
138 CLK_USBCTRL_FDBK_PLUS1(192 - 1));
139 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_POSTDIV_2POW(0x01));
140 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_PLL_PWRUP);
141
142 ret = wait_for_bit_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_PLL_STS,
143 true, CONFIG_SYS_HZ, false);
144 if (ret)
145 return ret;
146
147 /* enable PLL output */
148 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_CLK_EN2);
149
150 return 0;
151 }
152
usb_cpu_init(void)153 int usb_cpu_init(void)
154 {
155 u32 ret;
156 struct udevice *dev = NULL;
157
158 #if CONFIG_IS_ENABLED(DM_I2C)
159 ret = i2c_get_chip_for_busnum(I2C_2, ISP1301_I2C_ADDR, 1, &dev);
160 if (ret) {
161 debug("%s: No bus %d\n", __func__, I2C_2);
162 return ret;
163 }
164 #endif
165
166 /*
167 * USB pins routing setup is done by "lpc32xx_usb_init()" and should
168 * be call by board "board_init()" or "misc_init_r()" functions.
169 */
170
171 /* enable AHB slave USB clock */
172 setbits_le32(&clk_pwr->usb_ctrl,
173 CLK_USBCTRL_HCLK_EN | CLK_USBCTRL_BUS_KEEPER);
174
175 /* enable I2C clock */
176 writel(OTG_CLK_I2C_EN, &otg->otg_clk_ctrl);
177 ret = wait_for_bit_le32(&otg->otg_clk_sts, OTG_CLK_I2C_EN, true,
178 CONFIG_SYS_HZ, false);
179 if (ret)
180 return ret;
181
182 /* Configure ISP1301 */
183 isp1301_configure(dev);
184
185 /* setup USB clocks and PLL */
186 ret = usbpll_setup();
187 if (ret)
188 return ret;
189
190 /* enable usb_host_need_clk */
191 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_USBHSTND_EN);
192
193 /* enable all needed USB clocks */
194 const u32 mask = OTG_CLK_AHB_EN | OTG_CLK_OTG_EN |
195 OTG_CLK_I2C_EN | OTG_CLK_HOST_EN;
196 writel(mask, &otg->otg_clk_ctrl);
197
198 ret = wait_for_bit_le32(&otg->otg_clk_sts, mask, true,
199 CONFIG_SYS_HZ, false);
200 if (ret)
201 return ret;
202
203 setbits_le32(&otg->otg_sts_ctrl, OTG_HOST_EN);
204 isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_SET, OTG1_VBUS_DRV);
205
206 return 0;
207 }
208
usb_cpu_stop(void)209 int usb_cpu_stop(void)
210 {
211 struct udevice *dev = NULL;
212 int ret = 0;
213
214 #if CONFIG_IS_ENABLED(DM_I2C)
215 ret = i2c_get_chip_for_busnum(I2C_2, ISP1301_I2C_ADDR, 1, &dev);
216 if (ret) {
217 debug("%s: No bus %d\n", __func__, I2C_2);
218 return ret;
219 }
220 #endif
221
222 /* vbus off */
223 isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_SET, OTG1_VBUS_DRV);
224
225 clrbits_le32(&otg->otg_sts_ctrl, OTG_HOST_EN);
226
227 clrbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_HCLK_EN);
228
229 return ret;
230 }
231
usb_cpu_init_fail(void)232 int usb_cpu_init_fail(void)
233 {
234 return usb_cpu_stop();
235 }
236