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Searched refs:pcie (Results 1 – 25 of 45) sorted by relevance

12

/drivers/pci/
A Dpcie_layerscape_gen4.c192 if (!pcie->enabled) in ls_pcie_g4_addr_valid()
459 pcie->bus = dev; in ls_pcie_g4_probe()
468 pcie->idx = (pcie->ccsr_res.start - PCIE_SYS_BASE_ADDR) / in ls_pcie_g4_probe()
473 pcie->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx)); in ls_pcie_g4_probe()
474 if (!pcie->enabled) { in ls_pcie_g4_probe()
480 pcie->ccsr = map_physmem(pcie->ccsr_res.start, in ls_pcie_g4_probe()
498 pcie->cfg = map_physmem(pcie->cfg_res.start, in ls_pcie_g4_probe()
509 pcie->lut = map_physmem(pcie->lut_res.start, in ls_pcie_g4_probe()
520 pcie->pf_ctrl = map_physmem(pcie->pf_ctrl_res.start, in ls_pcie_g4_probe()
527 dev->name, (unsigned long)pcie->ccsr, (unsigned long)pcie->cfg, in ls_pcie_g4_probe()
[all …]
A Dpci_mvebu.c264 mvebu_pcie_set_local_bus_nr(pcie, pcie->sec_busno); in mvebu_pcie_write_config()
358 writel(pcie->intregs, pcie->base + MVPCIE_BAR_LO_OFF(0)); in mvebu_pcie_setup_wins()
530 pcie->mem.start, pcie->mem.start, in mvebu_pcie_probe()
538 pcie->io.start, pcie->io.start, in mvebu_pcie_probe()
637 sprintf(pcie->name, "pcie%d.%d", pcie->port, pcie->lane); in mvebu_pcie_port_parse_dt()
653 &pcie->mem_target, &pcie->mem_attr); in mvebu_pcie_port_parse_dt()
661 &pcie->io_target, &pcie->io_attr); in mvebu_pcie_port_parse_dt()
676 pcie->intregs = (u32)pcie->base - fdt32_to_cpu(addr[2]); in mvebu_pcie_port_parse_dt()
747 pcie = calloc(1, sizeof(*pcie)); in mvebu_pcie_bind()
748 if (!pcie) in mvebu_pcie_bind()
[all …]
A Dpcie_layerscape.c25 return in_le32(pcie->dbi + offset); in dbi_readl()
30 out_le32(pcie->dbi + offset, value); in dbi_writel()
35 if (pcie->big_endian) in ctrl_readl()
36 return in_be32(pcie->ctrl + offset); in ctrl_readl()
44 if (pcie->big_endian) in ctrl_writel()
55 val = dbi_readl(pcie, reg); in ls_pcie_dbi_ro_wr_en()
57 dbi_writel(pcie, val, reg); in ls_pcie_dbi_ro_wr_en()
65 val = dbi_readl(pcie, reg); in ls_pcie_dbi_ro_wr_dis()
67 dbi_writel(pcie, val, reg); in ls_pcie_dbi_ro_wr_dis()
77 state = ctrl_readl(pcie, LS1021_PEXMSCPORTSR(pcie->idx)); in ls_pcie_ltssm()
[all …]
A Dpci-aardvark.c171 writel(val, pcie->base + reg); in advk_writel()
176 return readl(pcie->base + reg); in advk_readl()
401 if (pcie->cfgcrssve) in pcie_advk_read_config()
430 dev_err(pcie->dev, in pcie_advk_read_config()
443 if (busno == pcie->sec_busno) in pcie_advk_read_config()
591 dev_err(pcie->dev, in pcie_advk_write_config()
599 if (busno == pcie->sec_busno) in pcie_advk_write_config()
724 dev_dbg(pcie->dev, in pcie_advk_set_ob_region()
739 dev_err(pcie->dev, in pcie_advk_set_ob_region()
895 pcie_advk_wait_for_link(pcie); in pcie_advk_setup_hw()
[all …]
A Dpcie_cdns_ti.c501 pcie_cdns_ti_rp_writew(pcie, PCI_DEVICE_ID, pcie->device_id); in pcie_cdns_ti_init_root_port()
642 pcie->io.size); in pcie_cdns_ti_init_address_translation()
651 pcie->mem.size); in pcie_cdns_ti_init_address_translation()
702 pcie->dev = dev; in pcie_cdns_ti_probe()
709 pcie->mode = data->mode; in pcie_cdns_ti_probe()
782 if (!pcie->intd_cfg_base) in pcie_cdns_ti_of_to_plat()
786 if (!pcie->user_cfg_base) in pcie_cdns_ti_of_to_plat()
790 if (!pcie->reg_base) in pcie_cdns_ti_of_to_plat()
794 if (!pcie->cfg_base) in pcie_cdns_ti_of_to_plat()
797 pcie->vendor_id = 0xffff; in pcie_cdns_ti_of_to_plat()
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A Dpcie_layerscape_rc.c31 struct ls_pcie *pcie = pcie_rc->pcie; in ls_pcie_cfg0_set_busdev() local
40 struct ls_pcie *pcie = pcie_rc->pcie; in ls_pcie_cfg1_set_busdev() local
51 struct ls_pcie *pcie = pcie_rc->pcie; in ls_pcie_setup_atu() local
131 struct ls_pcie *pcie = pcie_rc->pcie; in ls_pcie_addr_valid() local
155 struct ls_pcie *pcie = pcie_rc->pcie; in ls_pcie_conf_address() local
199 struct ls_pcie *pcie = pcie_rc->pcie; in ls_pcie_clear_multifunction() local
207 struct ls_pcie *pcie = pcie_rc->pcie; in ls_pcie_fix_class() local
215 struct ls_pcie *pcie = pcie_rc->pcie; in ls_pcie_drop_msg_tlp() local
266 pcie_rc->pcie = pcie; in ls_pcie_probe()
320 pcie->ctrl = pcie->lut; in ls_pcie_probe()
[all …]
A Dpcie_intel_fpga.c40 #define RP_CFG_ADDR(pcie, reg) \ argument
42 #define RP_SECONDARY(pcie) \ argument
46 #define TLP_CFGRD_DW0(pcie, bus) \ argument
51 #define TLP_CFGWR_DW0(pcie, bus) \ argument
67 #define IS_ROOT_PORT(pcie, bdf) \ argument
125 if (!IS_ROOT_PORT(pcie, bdf) && !intel_fpga_pcie_link_up(pcie)) in intel_fpga_pcie_addr_valid()
192 tlp_write_tx(pcie, headers[1], 0); in tlp_write_packet()
194 tlp_write_tx(pcie, headers[2], 0); in tlp_write_packet()
288 if (IS_ROOT_PORT(pcie, bdf)) in _pcie_intel_fpga_read_config()
318 if (IS_ROOT_PORT(pcie, bdf)) in _pcie_intel_fpga_write_config()
[all …]
A Dpcie_fsl.c31 if (!pcie->enabled) in fsl_pcie_addr_valid()
37 if (PCI_BUS(bdf) > dev_seq(bus) && (!fsl_pcie_link_up(pcie) || pcie->mode)) in fsl_pcie_addr_valid()
577 pcie->bus = dev; in fsl_pcie_probe()
581 pcie->enabled = is_serdes_configured(PCIE1 + pcie->idx); in fsl_pcie_probe()
582 if (!pcie->enabled) { in fsl_pcie_probe()
589 pcie->mode = fsl_pcie_is_agent(pcie); in fsl_pcie_probe()
595 if (pcie->mode) { in fsl_pcie_probe()
597 fsl_pcie_init_ep(pcie); in fsl_pcie_probe()
600 fsl_pcie_init_rc(pcie); in fsl_pcie_probe()
621 if (!pcie->regs) { in fsl_pcie_of_to_plat()
[all …]
A Dpcie-xilinx-nwl.c145 addr = pcie->ecam_base; in nwl_pcie_config_address()
227 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base), in nwl_pcie_bridge_init()
229 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base), in nwl_pcie_bridge_init()
237 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX0) | in nwl_pcie_bridge_init()
258 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) | in nwl_pcie_bridge_init()
261 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) | in nwl_pcie_bridge_init()
265 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base), in nwl_pcie_bridge_init()
267 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base), in nwl_pcie_bridge_init()
279 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MISC_STATUS) & in nwl_pcie_bridge_init()
286 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) & in nwl_pcie_bridge_init()
[all …]
A Dpcie_iproc.c463 if (!pcie->link_is_active) in iproc_pcie_map_ep_cfg_reg()
659 switch (pcie->type) { in iproc_pcie_rev_init()
669 if (pcie->need_ob_cfg) { in iproc_pcie_rev_init()
685 if (!pcie->reg_offsets) in iproc_pcie_rev_init()
689 pcie->reg_offsets[0] = (pcie->type == IPROC_PCIE_PAXC_V2) ? in iproc_pcie_rev_init()
1040 dev_dbg(pcie->dev, in iproc_pcie_map_dma_ranges()
1176 if (!pcie->base) in iproc_pcie_probe()
1182 pcie->dev = dev; in iproc_pcie_probe()
1204 iproc_pcie_reset(pcie); in iproc_pcie_probe()
1206 if (pcie->need_ob_cfg) { in iproc_pcie_probe()
[all …]
A Dpci_tegra.c197 struct tegra_pcie *pcie; member
301 *address = pcie->cs.start + in tegra_pcie_conf_address()
513 if (pcie->phy) { in tegra_pcie_parse_dt()
552 port->pcie = pcie; in tegra_pcie_parse_dt()
556 &pcie->xbar); in tegra_pcie_parse_dt()
731 if (pcie->phy) {
761 if (pcie->phy)
807 axi = pcie->cs.start;
918 struct tegra_pcie *pcie = port->pcie; local
924 value = afi_readl(pcie, ctrl);
[all …]
A Dpcie_layerscape_gen4_fixup.c66 pcie->ccsr_res.start); in fdt_pcie_set_msi_map_entry_ls_gen4()
110 pcie->ccsr_res.start); in fdt_pcie_set_iommu_map_entry_ls_gen4()
142 struct ls_pcie_g4 *pcie; in fdt_fixup_pcie_ls_gen4() local
151 pcie = dev_get_priv(bus); in fdt_fixup_pcie_ls_gen4()
153 streamid = pcie_next_streamid(pcie->stream_id_cur, pcie->idx); in fdt_fixup_pcie_ls_gen4()
158 pcie->stream_id_cur++; in fdt_fixup_pcie_ls_gen4()
194 if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_NORMAL) in ft_pcie_ep_layerscape_gen4_fix()
215 if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE) in ft_pcie_rc_layerscape_gen4_fix()
226 pcie->stream_id_cur = 0; in ft_pcie_layerscape_gen4_setup()
227 pcie->next_lut_index = 0; in ft_pcie_layerscape_gen4_setup()
[all …]
A Dpcie_dw_mvebu.c272 if (pcie->region_count > 1) in pcie_dw_mvebu_read_config()
275 pcie->io.bus_start, pcie->io.size); in pcie_dw_mvebu_read_config()
318 if (pcie->region_count > 1) in pcie_dw_mvebu_write_config()
321 pcie->io.bus_start, pcie->io.size); in pcie_dw_mvebu_write_config()
533 pcie->mem.phys_start = hose->regions[pcie->region_count - 1].phys_start; in pcie_dw_mvebu_probe()
535 pcie->mem.bus_start = hose->regions[pcie->region_count - 1].bus_start; in pcie_dw_mvebu_probe()
537 pcie->mem.size = hose->regions[pcie->region_count - 1].size; in pcie_dw_mvebu_probe()
541 pcie->mem.bus_start, pcie->mem.size); in pcie_dw_mvebu_probe()
569 if (!pcie->ctrl_base) in pcie_dw_mvebu_of_to_plat()
574 &pcie->cfg_size); in pcie_dw_mvebu_of_to_plat()
[all …]
A Dpcie_layerscape_ep.c23 struct ls_pcie *pcie = pcie_ep->pcie; in ls_pcie_ep_enable_cfg() local
34 struct ls_pcie *pcie = pcie_ep->pcie; in ls_ep_set_bar() local
71 struct ls_pcie *pcie = pcie_ep->pcie; in ls_pcie_ep_setup_atu() local
187 struct ls_pcie *pcie = pcie_ep->pcie; in ls_pcie_setup_ep() local
247 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); in ls_pcie_ep_probe()
248 if (!pcie) in ls_pcie_ep_probe()
251 pcie_ep->pcie = pcie; in ls_pcie_ep_probe()
254 if (!pcie->dbi) in ls_pcie_ep_probe()
258 if (!pcie->ctrl) in ls_pcie_ep_probe()
269 pcie->idx = ((unsigned long)pcie->dbi - PCIE_SYS_BASE_ADDR) / in ls_pcie_ep_probe()
[all …]
A Dpcie_mediatek_gen3.c306 if (!pcie->base) in mtk_pcie_power_on()
309 pcie->priv = dev; in mtk_pcie_power_on()
334 if (pcie->phy.dev) { in mtk_pcie_power_on()
348 err = clk_enable(&pcie->tl_26m_ck); in mtk_pcie_power_on()
368 clk_disable(&pcie->top_133m_ck); in mtk_pcie_power_on()
370 clk_disable(&pcie->peri_26m_ck); in mtk_pcie_power_on()
372 clk_disable(&pcie->tl_26m_ck); in mtk_pcie_power_on()
374 clk_disable(&pcie->pl_250m_ck); in mtk_pcie_power_on()
376 if (pcie->phy.dev) in mtk_pcie_power_on()
377 generic_phy_exit(&pcie->phy); in mtk_pcie_power_on()
[all …]
A Dpcie_ecam_synquacer.c236 addr = pcie->cfg_base; in pci_synquacer_ecam_conf_address()
348 if (!pcie->dbi_base) { in pci_synquacer_ecam_of_to_plat()
355 if (!pcie->exs_base) { in pci_synquacer_ecam_of_to_plat()
361 pcie->cfg_base = map_physmem(reg_res.start, pcie->size, MAP_NOCACHE); in pci_synquacer_ecam_of_to_plat()
362 if (!pcie->cfg_base) { in pci_synquacer_ecam_of_to_plat()
366 debug("mappings DBI: %p EXS: %p CFG: %p\n", pcie->dbi_base, pcie->exs_base, pcie->cfg_base); in pci_synquacer_ecam_of_to_plat()
502 pcie->mem.size, in pci_synquacer_post_init()
519 (u64)pcie->io.phys_start - (u64)pcie->cfg_base - SIZE_64KB, in pci_synquacer_post_init()
526 pcie->io.bus_start, in pci_synquacer_post_init()
527 pcie->io.size, in pci_synquacer_post_init()
[all …]
A Dpcie_layerscape_gen4.h200 if (pcie->big_endian) in lut_writel()
201 out_be32(pcie->lut + offset, value); in lut_writel()
203 out_le32(pcie->lut + offset, value); in lut_writel()
208 if (pcie->big_endian) in lut_readl()
209 return in_be32(pcie->lut + offset); in lut_readl()
211 return in_le32(pcie->lut + offset); in lut_readl()
218 val = in_le32(pcie->ccsr + PAB_CTRL); in ccsr_set_page()
228 ccsr_set_page(pcie, 0); in ccsr_readl()
239 ccsr_set_page(pcie, 0); in ccsr_writel()
249 if (pcie->big_endian) in pf_ctrl_readl()
[all …]
A Dpcie_xilinx.c68 struct xilinx_pcie *pcie = dev_get_priv(udev); in pcie_xilinx_config_address() local
69 unsigned int bus = PCI_BUS(bdf) - pcie->first_busno; in pcie_xilinx_config_address()
72 int num_buses = DIV_ROUND_UP(pcie->size, 1 << 16); in pcie_xilinx_config_address()
75 if ((bus > 0) && !pcie_xilinx_link_up(pcie)) in pcie_xilinx_config_address()
88 addr = pcie->cfg_base; in pcie_xilinx_config_address()
151 struct xilinx_pcie *pcie = dev_get_priv(dev); in pcie_xilinx_of_to_plat() local
160 if (!pcie->cfg_base) in pcie_xilinx_of_to_plat()
162 pcie->size = size; in pcie_xilinx_of_to_plat()
168 struct xilinx_pcie *pcie = dev_get_priv(dev); in pci_xilinx_probe() local
172 pcie->first_busno = dev_seq(dev); in pci_xilinx_probe()
[all …]
A Dpcie_apple.c151 struct apple_pcie_priv *pcie; member
177 addr = pcie->cfg_base; in apple_pcie_config_address()
215 if (pcie->hw->phy_lane_ctl) in apple_pcie_setup_refclk()
234 if (pcie->hw->phy_lane_ctl) in apple_pcie_setup_refclk()
239 if (pcie->hw->port_refclk) in apple_pcie_setup_refclk()
268 port->pcie = pcie; in apple_pcie_setup_port()
324 if (pcie->hw->port_refclk) in apple_pcie_setup_port()
342 pcie->dev = dev; in apple_pcie_probe()
346 pcie->cfg_base = map_sysmem(addr, 0); in apple_pcie_probe()
351 pcie->base = map_sysmem(addr, 0); in apple_pcie_probe()
[all …]
A Dpcie_ecam_generic.c47 struct generic_ecam_pcie *pcie = dev_get_priv(bus); in pci_generic_ecam_conf_address() local
50 addr = pcie->cfg_base; in pci_generic_ecam_conf_address()
53 addr += ((PCI_BUS(bdf) - pcie->first_busno) << 16) | in pci_generic_ecam_conf_address()
67 struct generic_ecam_pcie *pcie = dev_get_priv(bus); in pci_generic_ecam_addr_valid() local
68 int num_buses = DIV_ROUND_UP(pcie->size, 1 << 16); in pci_generic_ecam_addr_valid()
70 return (PCI_BUS(bdf) >= pcie->first_busno && in pci_generic_ecam_addr_valid()
71 PCI_BUS(bdf) < pcie->first_busno + num_buses); in pci_generic_ecam_addr_valid()
134 struct generic_ecam_pcie *pcie = dev_get_priv(dev); in pci_generic_ecam_of_to_plat() local
145 pcie->size = resource_size(&reg_res); in pci_generic_ecam_of_to_plat()
146 pcie->cfg_base = map_physmem(reg_res.start, pcie->size, MAP_NOCACHE); in pci_generic_ecam_of_to_plat()
[all …]
A Dpcie_brcmstb.c142 *paddress = pcie->base + offset; in brcm_pcie_config_address()
147 if (!brcm_pcie_link_up(pcie)) in brcm_pcie_config_address()
312 void __iomem *base = pcie->base; in brcm_pcie_set_outbound_win()
425 if (pcie->gen) in brcm_pcie_probe()
426 brcm_pcie_set_gen(pcie, pcie->gen); in brcm_pcie_probe()
444 if (!brcm_pcie_link_up(pcie)) { in brcm_pcie_probe()
449 if (!brcm_pcie_rc_mode(pcie)) { in brcm_pcie_probe()
476 if (pcie->ssc) { in brcm_pcie_probe()
538 if (!pcie->base) in brcm_pcie_of_to_plat()
545 pcie->gen = 0; in brcm_pcie_of_to_plat()
[all …]
A Dpci_octeontx.c109 *valuep = readl_size(pcie->cfg.start + address, size); in octeontx_ecam_read_config()
127 writel_size(pcie->cfg.start + address, size, value); in octeontx_ecam_write_config()
143 u8 pri_bus = pcie->bus.start + 1 - hose->first_busno; in octeontx_pem_read_config()
173 u8 pri_bus = pcie->bus.start + 1 - hose->first_busno; in octeontx_pem_write_config()
213 *valuep = readl_size(pcie->cfg.start + address, size); in octeontx2_pem_read_config()
235 writel_size(pcie->cfg.start + address, size, value); in octeontx2_pem_write_config()
251 switch (pcie->type) { in pci_octeontx_read_config()
276 switch (pcie->type) { in pci_octeontx_write_config()
304 pcie->type = dev_get_driver_data(dev); in pci_octeontx_probe()
306 err = dev_read_resource(dev, 0, &pcie->cfg); in pci_octeontx_probe()
[all …]
/drivers/pci_endpoint/
A Dpcie_cdns_ti_ep.c128 pcie->max_link_speed - 1); in pcie_cdns_ti_ctrl_init()
132 (pcie->num_lanes - 1) << 8); in pcie_cdns_ti_ctrl_init()
140 struct cdns_pcie pcie; in pcie_cdns_ti_write_header() local
177 struct cdns_pcie pcie; in pcie_cdns_ti_set_bar() local
256 pcie_cdns_ti_start_link(pcie); in pcie_cdns_ti_start()
269 pcie->dev = dev; in pcie_cdns_ti_ep_probe()
330 if (!pcie->intd_cfg_base) in pcie_cdns_ti_ep_of_to_plat()
334 if (!pcie->user_cfg_base) in pcie_cdns_ti_ep_of_to_plat()
338 if (!pcie->reg_base) in pcie_cdns_ti_ep_of_to_plat()
342 if (!pcie->mem_base) in pcie_cdns_ti_ep_of_to_plat()
[all …]
A Dpcie-cadence.h238 writeb(value, pcie->reg_base + reg); in cdns_pcie_writeb()
243 writew(value, pcie->reg_base + reg); in cdns_pcie_writew()
248 writel(value, pcie->reg_base + reg); in cdns_pcie_writel()
253 return readl(pcie->reg_base + reg); in cdns_pcie_readl()
257 static inline void cdns_pcie_rp_writeb(struct cdns_pcie *pcie, in cdns_pcie_rp_writeb() argument
260 writeb(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg); in cdns_pcie_rp_writeb()
263 static inline void cdns_pcie_rp_writew(struct cdns_pcie *pcie, in cdns_pcie_rp_writew() argument
266 writew(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg); in cdns_pcie_rp_writew()
269 static inline void cdns_pcie_rp_writel(struct cdns_pcie *pcie, in cdns_pcie_rp_writel() argument
272 writel(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg); in cdns_pcie_rp_writel()
[all …]
A Dpcie-cadence-ep.c20 struct cdns_pcie *pcie = dev_get_priv(dev); in cdns_write_header() local
24 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CLASS_PROG, in cdns_write_header()
26 cdns_pcie_ep_fn_writew(pcie, fn, PCI_CLASS_DEVICE, in cdns_write_header()
29 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CACHE_LINE_SIZE, in cdns_write_header()
31 cdns_pcie_ep_fn_writew(pcie, fn, PCI_SUBSYSTEM_ID, in cdns_write_header()
33 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_INTERRUPT_PIN, in cdns_write_header()
45 cdns_pcie_writel(pcie, CDNS_PCIE_LM_ID, id); in cdns_write_header()
53 struct cdns_pcie *pcie = dev_get_priv(dev); in cdns_set_bar() local
107 cfg = cdns_pcie_readl(pcie, reg); in cdns_set_bar()
112 cdns_pcie_writel(pcie, reg, cfg); in cdns_set_bar()
[all …]

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