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Searched refs:phy_base (Results 1 – 17 of 17) sorted by relevance

/drivers/ram/rockchip/
A Dsdram_phy_px30.c23 setbits_le32(PHY_REG(phy_base, j), 1 << 4); in sdram_phy_dll_bypass_set()
46 writel(tmp, PHY_REG(phy_base, j)); in sdram_phy_dll_bypass_set()
71 writel(cmd_drv, PHY_REG(phy_base, 0x11)); in sdram_phy_set_ds_odt()
73 writel(clk_drv, PHY_REG(phy_base, 0x16)); in sdram_phy_set_ds_odt()
74 writel(clk_drv, PHY_REG(phy_base, 0x18)); in sdram_phy_set_ds_odt()
78 writel(dqs_drv, PHY_REG(phy_base, j)); in sdram_phy_set_ds_odt()
113 phy_soft_reset(phy_base); in phy_dram_set_bw()
127 writel(0, PHY_REG(phy_base, j + 0xe)); in phy_data_training()
141 ret = readl(PHY_REG(phy_base, 0xff)); in phy_data_training()
170 void phy_cfg(void __iomem *phy_base, in phy_cfg() argument
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A Dsdram_rv1126.c542 void __iomem *phy_base = dram->phy; in phy_pll_set() local
1206 PHY_REG(phy_base, 0x4f)); in sdram_cmd_dq_path_remap()
1352 writel(tmp, PHY_REG(phy_base, in record_dq_prebit()
1359 writel(tmp, PHY_REG(phy_base, in record_dq_prebit()
1472 readl(PHY_REG(phy_base, in get_min_value()
1558 PHY_REG(phy_base, j)); in data_training_rg()
1722 PHY_REG(phy_base, 0x238 + i)); in data_training_rd()
1725 PHY_REG(phy_base, 0x2b8 + i)); in data_training_rd()
2852 phy_base + phy_offset + in pre_set_rate()
2879 PHY_REG(phy_base, 0x19)); in pre_set_rate()
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A Dsdram_rk3328.c122 void __iomem *phy_base = dram->phy; in rkclk_configure_ddr() local
125 clrbits_le32(PHY_REG(phy_base, 0xef), 1 << 7); in rkclk_configure_ddr()
261 void __iomem *phy_base = dram->phy; in rx_deskew_switch_adjust() local
264 gate_val = MAX(readl(PHY_REG(phy_base, 0xfb + i)), gate_val); in rx_deskew_switch_adjust()
268 clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0xc, (deskew_val & 0x3) << 2); in rx_deskew_switch_adjust()
269 clrsetbits_le32(PHY_REG(phy_base, 0x6f), 0x7 << 4, in rx_deskew_switch_adjust()
275 void __iomem *phy_base = dram->phy; in tx_deskew_switch_adjust() local
277 clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0x3, 1); in tx_deskew_switch_adjust()
A Dsdram_px30.c318 void __iomem *phy_base = dram->phy; in check_rd_gate() local
325 bw = (readl(PHY_REG(phy_base, 0x0)) >> 4) & 0xf; in check_rd_gate()
340 gate[i] = readl(PHY_REG(phy_base, 0xfb + i)); in check_rd_gate()
436 void __iomem *phy_base = dram->phy; in enable_low_power() local
463 setbits_le32(PHY_REG(phy_base, 7), 1 << 7); in enable_low_power()
/drivers/pci/
A Dpci-rcar-gen4.c106 void *phy_base; member
191 setbits_le32(rcar->phy_base + 0x0f8, BIT(17)); in rcar_gen4_pcie_download_phy_firmware()
230 clrsetbits_le32(rcar->phy_base + 0x700, BIT(28), 0); in rcar_gen4_pcie_ltssm_control()
231 clrsetbits_le32(rcar->phy_base + 0x700, BIT(20), 0); in rcar_gen4_pcie_ltssm_control()
232 clrsetbits_le32(rcar->phy_base + 0x700, BIT(12), 0); in rcar_gen4_pcie_ltssm_control()
233 clrsetbits_le32(rcar->phy_base + 0x700, BIT(4), 0); in rcar_gen4_pcie_ltssm_control()
240 clrsetbits_le32(rcar->phy_base + 0x514, BIT(26), BIT(26)); in rcar_gen4_pcie_ltssm_control()
241 clrsetbits_le32(rcar->phy_base + 0x0f8, BIT(16), 0); in rcar_gen4_pcie_ltssm_control()
242 clrsetbits_le32(rcar->phy_base + 0x0f8, BIT(19), BIT(19)); in rcar_gen4_pcie_ltssm_control()
523 rcar->phy_base = (void *)dev_read_addr_name(dev, "phy"); in rcar_gen4_pcie_of_to_plat()
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/drivers/ddr/altera/
A Dsdram_n5x.c360 phys_addr_t phy_base; member
952 ddr_handoff_info->phy_base); in init_phy()
1096 (u32)handoff->phy_base); in populate_ddr_handoff()
1172 handoff->train_imem_base = handoff->phy_base + in populate_ddr_handoff()
1177 handoff->train_dmem_base = handoff->phy_base + in populate_ddr_handoff()
1403 setbits_le16(ddr_handoff_info->phy_base + in configure_training_firmware()
1498 *index = readw((uintptr_t)(handoff->phy_base + in get_mail_streaming()
1594 setbits_le16((uintptr_t)(handoff->phy_base + in enable_phy_clk_for_csr_access()
1600 clrbits_le16((uintptr_t)(handoff->phy_base + in enable_phy_clk_for_csr_access()
1677 val = (readw((uintptr_t)(handoff->phy_base + in get_max_txdqsdlytg0_ux_p0()
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/drivers/phy/
A Domap-usb2-phy.c47 void *phy_base; member
164 val = readl(priv->phy_base + USB2PHY_ANA_CONFIG1); in omap_usb2_phy_init()
166 writel(val, priv->phy_base + USB2PHY_ANA_CONFIG1); in omap_usb2_phy_init()
170 val = readl(priv->phy_base + USB2PHY_CHRG_DET); in omap_usb2_phy_init()
172 writel(val, priv->phy_base + USB2PHY_CHRG_DET); in omap_usb2_phy_init()
217 priv->phy_base = dev_read_addr_ptr(dev); in omap_usb2_phy_probe()
219 if (!priv->phy_base) in omap_usb2_phy_probe()
/drivers/net/mtk_eth/
A Dan8855.c265 u32 phy_base; member
322 ret = mtk_mii_write(priv, phy_base, 0x1f, 0x4); in __an8855_reg_read()
326 ret = mtk_mii_write(priv, phy_base, 0x10, 0); in __an8855_reg_read()
338 low_word = mtk_mii_read(priv, phy_base, 0x18); in __an8855_reg_read()
342 high_word = mtk_mii_read(priv, phy_base, 0x17); in __an8855_reg_read()
346 ret = mtk_mii_write(priv, phy_base, 0x1f, 0); in __an8855_reg_read()
350 ret = mtk_mii_write(priv, phy_base, 0x10, 0); in __an8855_reg_read()
411 u16 phy_addr = AN8855_PHY_ADDR(priv->phy_base, port); in an8855_phy_cl45_read()
981 priv->phy_base = 1; in an8855_setup()
985 phy_addr = AN8855_PHY_ADDR(priv->phy_base, i); in an8855_setup()
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A Dmt7531.c25 u8 phy_addr = MT753X_PHY_ADDR(priv->phy_base, 0); in mt7531_core_reg_read()
33 u8 phy_addr = MT753X_PHY_ADDR(priv->phy_base, 0); in mt7531_core_reg_write()
177 priv->phy_base = (priv->smi_addr + 1) & MT753X_SMI_ADDR_MASK; in mt7531_setup()
183 phy_addr = MT753X_PHY_ADDR(priv->phy_base, i); in mt7531_setup()
242 phy_addr = MT753X_PHY_ADDR(priv->phy_base, i); in mt7531_setup()
A Dmt7988.c69 priv->phy_base = (priv->smi_addr + 1) & MT753X_SMI_ADDR_MASK; in mt7988_setup()
75 phy_addr = MT753X_PHY_ADDR(priv->phy_base, i); in mt7988_setup()
131 phy_addr = MT753X_PHY_ADDR(priv->phy_base, i); in mt7988_setup()
A Dmt753x.c139 phy_addr = MT753X_PHY_ADDR(priv->phy_base, phy); in mt7531_mii_read()
152 phy_addr = MT753X_PHY_ADDR(priv->phy_base, phy); in mt7531_mii_write()
167 phy_addr = MT753X_PHY_ADDR(priv->phy_base, addr); in mt7531_mmd_read()
187 phy_addr = MT753X_PHY_ADDR(priv->phy_base, addr); in mt7531_mmd_write()
A Dmt7530.c25 u8 phy_addr = MT753X_PHY_ADDR(priv->phy_base, 0); in mt7530_core_reg_write()
176 priv->phy_base = (val | 0x7) + 1; in mt7530_setup()
180 phy_addr = MT753X_PHY_ADDR(priv->phy_base, i); in mt7530_setup()
238 phy_addr = MT753X_PHY_ADDR(priv->phy_base, i); in mt7530_setup()
A Dmt753x.h259 u32 phy_base; member
/drivers/usb/host/
A Dxhci-exynos5.c39 fdt_addr_t phy_base; member
82 plat->phy_base = fdtdec_get_addr(blob, node, "reg"); in xhci_usb_of_to_plat()
83 if (plat->phy_base == FDT_ADDR_T_NONE) { in xhci_usb_of_to_plat()
214 ctx->usb3_phy = (struct exynos_usb3_phy *)plat->phy_base; in xhci_usb_probe()
A Dehci-exynos.c32 fdt_addr_t phy_base; member
73 plat->phy_base = fdtdec_get_addr(blob, node, "reg"); in ehci_usb_of_to_plat()
74 if (plat->phy_base == FDT_ADDR_T_NONE) { in ehci_usb_of_to_plat()
222 ctx->usb = (struct exynos_usb_phy *)plat->phy_base; in ehci_usb_probe()
/drivers/phy/rockchip/
A Dphy-rockchip-inno-dsidphy.c215 void __iomem *phy_base; member
293 orig = readl(inno->phy_base + reg); in phy_update_bits()
296 writel(tmp, inno->phy_base + reg); in phy_update_bits()
627 inno->phy_base = dev_read_addr_ptr(dev); in inno_dsidphy_probe()
628 if (IS_ERR(inno->phy_base)) in inno_dsidphy_probe()
629 return PTR_ERR(inno->phy_base); in inno_dsidphy_probe()
A Dphy-rockchip-inno-usb2.c49 struct regmap *phy_base; member
178 *base = priv->phy_base; in rockchip_usb2phy_clkout_ctl()
305 ret = regmap_init_mem_index(dev_ofnode(dev), &priv->phy_base, 0); in rockchip_usb2phy_probe()

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