Searched refs:phy_ctl (Results 1 – 3 of 3) sorted by relevance
47 unsigned phy_ctl; in ksz90xx_startup() local54 phy_ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ90xx_PHY_CTL); in ksz90xx_startup()56 if (phy_ctl & MIIM_KSZ90xx_PHYCTL_DUPLEX) in ksz90xx_startup()61 if (phy_ctl & MIIM_KSZ90xx_PHYCTL_1000) in ksz90xx_startup()63 else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_100) in ksz90xx_startup()65 else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_10) in ksz90xx_startup()
998 phy_ctl.u64 = in get_deskew_settings()1065 phy_ctl.s.phy_reset = 0; in override_deskew_settings()1067 phy_ctl.s.dsk_dbg_offset = 0; in override_deskew_settings()1074 phy_ctl.s.phy_dsk_reset = 0; in override_deskew_settings()3740 phy_ctl.s.ts_stagger = 0; in lmc_phy_ctl()3746 phy_ctl.s.c0_sel = 2; in lmc_phy_ctl()3747 phy_ctl.s.c1_sel = 2; in lmc_phy_ctl()3753 phy_ctl.u64); in lmc_phy_ctl()9987 phy_ctl.s.phy_reset = 1; in test_dram_byte_hw()10081 phy_ctl.s.phy_reset = 1; in test_dram_byte_hw()[all …]
167 u32 val, phy_ctl; in pcie_phy_read() local175 phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC; in pcie_phy_read()176 writel(phy_ctl, dbi_base + PCIE_PHY_CTRL); in pcie_phy_read()
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