| /drivers/ram/starfive/ |
| A D | starfive_ddr.c | 27 void __iomem *phyreg; member
56 ddr_phy_train(priv->phyreg + (PHY_BASE_ADDR << 2)); in starfive_ddr_setup()
57 ddr_phy_util(priv->phyreg + (PHY_AC_BASE_ADDR << 2)); in starfive_ddr_setup()
58 ddr_phy_start(priv->phyreg, size); in starfive_ddr_setup()
62 priv->phyreg, size); in starfive_ddr_setup()
87 priv->phyreg = (void __iomem *)addr; in starfive_ddr_probe()
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| A D | ddrphy_utils.c | 1945 void ddr_phy_util(u32 *phyreg) in ddr_phy_util() argument
1951 out_le32(phyreg + i, ddr_phy_data[i]); in ddr_phy_util()
1954 out_le32(phyreg + i, ddr_phy_data[i]); in ddr_phy_util()
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| A D | starfive_ddr.h | 54 void ddr_phy_train(u32 *phyreg);
55 void ddr_phy_util(u32 *phyreg);
56 void ddr_phy_start(u32 *phyreg, enum ddr_size_t size);
57 void ddrcsr_boot(u32 *csrreg, u32 *secreg, u32 *phyreg, enum ddr_size_t size);
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| A D | ddrcsr_boot.c | 214 void ddrcsr_boot(u32 *csrreg, u32 *secreg, u32 *phyreg, enum ddr_size_t size) in ddrcsr_boot() argument
302 val = in_le32(phyreg + 1); in ddrcsr_boot()
319 out_le32(phyreg + 2, 0x1); in ddrcsr_boot()
320 ret = wait_for_bit_le32(phyreg + 2, BIT(0), false, 1000, false); in ddrcsr_boot()
329 val = in_le32(phyreg + 2048 + 83); in ddrcsr_boot()
330 val = in_le32(phyreg + 2048 + 84); in ddrcsr_boot()
331 out_le32(phyreg + 2048 + 84, val & 0xF8000000); in ddrcsr_boot()
334 ddr_csr_set(phyreg + PHY_BASE_ADDR, secreg, ddr_csr_cfg2, len, mask); in ddrcsr_boot()
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| A D | ddrphy_train.c | 376 void ddr_phy_train(u32 *phyreg) in ddr_phy_train() argument
382 out_le32(phyreg + i, ddr_train_data[i]); in ddr_phy_train()
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| A D | ddrphy_start.c | 252 void ddr_phy_start(u32 *phyreg, enum ddr_size_t size) in ddr_phy_start() argument
276 ddr_reg_set(phyreg, ddr_start_cfg, len, mask); in ddr_phy_start()
277 out_le32(phyreg, 0x01); in ddr_phy_start()
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| /drivers/net/ |
| A D | xilinx_emaclite.c | 257 u16 phyreg; in setup_phy() local
267 phyread(emaclite, emaclite->phyaddr, PHY_DETECT_REG, &phyreg); in setup_phy()
268 if ((phyreg != 0xFFFF) && in setup_phy()
269 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { in setup_phy()
283 phyread(emaclite, i, PHY_DETECT_REG, &phyreg); in setup_phy()
284 if ((phyreg != 0xFFFF) && in setup_phy()
285 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { in setup_phy()
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| A D | xilinx_axi_emac.c | 286 u16 phyreg; in axiemac_phy_init() local
316 ret = phyread(priv, i, PHY_DETECT_REG, &phyreg); in axiemac_phy_init()
317 if (!ret && (phyreg != 0xFFFF) && in axiemac_phy_init()
318 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { in axiemac_phy_init()
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| A D | dwc_eth_qos_intel.c | 72 unsigned char phyaddr, unsigned char phyreg, in serdes_status_poll() argument
80 miiphy_read(eqos->mii->name, phyaddr, phyreg, &val_rd); in serdes_status_poll()
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| A D | ag7xxx.c | 1203 int ret, phyreg; in ag7xxx_eth_probe() local
1209 phyreg = fdtdec_get_int(gd->fdt_blob, ret, "reg", -1); in ag7xxx_eth_probe()
1212 phyiobase = map_physmem(phyreg, 0x200, MAP_NOCACHE); in ag7xxx_eth_probe()
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| /drivers/ram/thead/ |
| A D | th1520_ddr.c | 501 static int th1520_ddr_read_msg(void __iomem *phyreg, u16 *id, u16 *data) in th1520_ddr_read_msg() argument
506 ret = readw_poll_timeout(phyreg + TH1520_PHY_MSG_STATUS, tmp, in th1520_ddr_read_msg()
512 *id = readw(phyreg + TH1520_PHY_MSG_ID); in th1520_ddr_read_msg()
513 *data = readw(phyreg + TH1520_PHY_MSG_DATA); in th1520_ddr_read_msg()
515 writew(0, phyreg + TH1520_PHY_MSG_ACK); in th1520_ddr_read_msg()
517 ret = readw_poll_timeout(phyreg + TH1520_PHY_MSG_STATUS, tmp, in th1520_ddr_read_msg()
523 writew(TH1520_PHY_MSG_ACK_EN, phyreg + TH1520_PHY_MSG_ACK); in th1520_ddr_read_msg()
528 static int th1520_phy_wait_pmu_completion(void __iomem *phyreg) in th1520_phy_wait_pmu_completion() argument
534 ret = th1520_ddr_read_msg(phyreg, &id, &data); in th1520_phy_wait_pmu_completion()
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